151 Odpowiedź przez ambrozy5

  • Zarejestrowany: 2015-01-28
  • Posty: 2,455

Odp: Router/firewall/NAS DIY na terminalu Fujitsu FUTRO S940. Czy się uda?

Bios najnowszy? Nie mam 940 ale na 920 to chyba wszystkie karty jakie mam śmigaly choć tam jest x4 stąd tak a nie inaczej.

Dom : router https://i.imgur.com/IuB6Zwy.png | TP-LINK T1700G-28TQ |Zyxel XGS-1210-12 | 6x Ruckus r310 unleashed  + Ruckus icx7150-c12p | Truenas scale 124TB 25Gb| Xpenology 12TB | apc smart ups 750 lcd smile 100Mb/s - 25Gb/s
Podróżne : GL.Inet MT3000  +1TB hdd
Działka : rb260gs 1j wdm 1Gb+ ruckus r310 + nb m5 + kilka kamer ip  + panel 285Wp + lifepo4 12v 60Ah .

152 Odpowiedź przez wrzoch

  • wrzoch
  • Użytkownik
  • Nieaktywny
  • Zarejestrowany: 2026-04-22
  • Posty: 2

Odp: Router/firewall/NAS DIY na terminalu Fujitsu FUTRO S940. Czy się uda?

ambrozy5 napisał/a:

Bios najnowszy? Nie mam 940 ale na 920 to chyba wszystkie karty jakie mam śmigaly choć tam jest x4 stąd tak a nie inaczej.

No właśnie BIOS najnowszy.

BIOS Update - Admin Pack for D3543-A1x
Title
D3543-A1x - Admin package - Compressed Flash FilesVersion (Publish date)
V5.0.0.13 - R1.14.0 (08/01/2025)
Released for FUTRO S940

Factory Reset po flashu, dalej to samo.
Oddałem ten pasywny riser, który do niego kupiłem.

A tak z ciekawości, bo obok PCIe, jest jakieś złącze, z wyprowadzonymi pinami równolegle na zewnątrz płyty. Co to?

153 Odpowiedź przez Adam1394 (edytowany przez Adam1394 2026-05-14 02:21:30)

  • Zarejestrowany: 2024-04-09
  • Posty: 28

Odp: Router/firewall/NAS DIY na terminalu Fujitsu FUTRO S940. Czy się uda?

1. Piny koło PCIe to slot na kartę internetową PoE (Power over Ethernet, zasilanie komputera z kabla RJ-45), ale taki moduł jest bardzo drogi i trudno dostępny (ponad 70€), całkowicie nieopłacalne. Jeśli spojrzysz na post nr 62 (trzecia strona) to @Bern wyciągnął z niego jedną linię PCIe (2.0).

2. Te złącza PCIe są bardzo kapryśne, u mnie na przykład nie działa karta Mellanox ConnectX-2 w ogóle. To co próbowałem:

a) różnie risery, najlepiej zadziałał u mnie miękki riser od chińczyka z Ali za 3-4 dolary, 15cm, 4x <-> 4x PCIe
b) różne karty, działa u mnie Intel X540 dwuportowy od Inspur (na Aliexpress za 15$) ALE(!!!) trzeba wyłączyć jeden port zworkami nad portami ethernet, przy dwóch portach włączonych karta nie działa, z jednym portem aktywnym nie ma problemu...
c) różne zasilacze, spróbuj inne voltarze zasilaczy, ten komputer śmiga bez problemu z zasilaczami w zakresie 9-20V, od siebie powiem że najmniejsze problemy są gdy mamy zasilacz 12V

Do tego dodałem kartę 5Gbit na złącze M.2 A+E z przejściówką na M.2 B+M, również to zależy od docisku karty do slotu, czasem nie łączy...

https://i.imgur.com/R2pgfPz.jpeg


edit: Już z chin leci mi przejściówka z wewnętrznego USB 2.0 (9pin) do zwykłego złącza USB, tak aby przewód od wentylatora na karcie Intel X540 10Gbit nie wychodził za obudowę, gorąco polecam taki wentylator bo karta się mocno grzeje.

Taki router potrafi przewalić okolice 3Gbit, przy czym hamulcowym są te 2 nieszczęsne porty PCIe x1 2.0, procesor jeszcze ma trochę zapasu...

154 Odpowiedź przez Mieze

  • Mieze
  • Użytkownik
  • Nieaktywny
  • Zarejestrowany: 2026-06-09
  • Posty: 4

Odp: Router/firewall/NAS DIY na terminalu Fujitsu FUTRO S940. Czy się uda?

I want to know to which PCIe port the PoE connector is routed. Could somebody, who is using this port to drive a PCIe device, please post the output of "lspci -vvv"?

155 Odpowiedź przez bern (edytowany przez bern 2026-06-10 11:45:43)

  • bern
  • Użytkownik
  • Nieaktywny
  • Zarejestrowany: 2012-04-17
  • Posty: 134

Odp: Router/firewall/NAS DIY na terminalu Fujitsu FUTRO S940. Czy się uda?

Mieze napisał/a:

I want to know to which PCIe port the PoE connector is routed. Could somebody, who is using this port to drive a PCIe device, please post the output of "lspci -vvv"?

Ja już nie używam FUTRO S940 bo przesiadłem się na ODROID H3+ ale wygrzebałem gdzieś z pudeł ten starszy sprzęt i odpaliłem.
Poniżej wyniki.
Wszystkie urządzenia pci:

el@akacja:~$ lspci
00:00.0 Host bridge: Intel Corporation Gemini Lake Host Bridge (rev 03)
00:00.1 Signal processing controller: Intel Corporation Celeron/Pentium Silver Processor Dynamic Platform and Thermal Framework Processor Participant (rev 03)
00:00.3 System peripheral: Intel Corporation Celeron/Pentium Silver Processor Gaussian Mixture Model (rev 03)
00:02.0 VGA compatible controller: Intel Corporation GeminiLake [UHD Graphics 605] (rev 03)
00:0e.0 Audio device: Intel Corporation Celeron/Pentium Silver Processor High Definition Audio (rev 03)
00:0f.0 Communication controller: Intel Corporation Celeron/Pentium Silver Processor Trusted Execution Engine Interface (rev 03)
00:12.0 SATA controller: Intel Corporation Celeron/Pentium Silver Processor SATA Controller (rev 03)
00:13.0 PCI bridge: Intel Corporation Gemini Lake PCI Express Root Port (rev f3)
00:13.1 PCI bridge: Intel Corporation Gemini Lake PCI Express Root Port (rev f3)
00:13.2 PCI bridge: Intel Corporation Gemini Lake PCI Express Root Port (rev f3)
00:13.3 PCI bridge: Intel Corporation Gemini Lake PCI Express Root Port (rev f3)
00:14.0 PCI bridge: Intel Corporation Gemini Lake PCI Express Root Port (rev f3)
00:14.1 PCI bridge: Intel Corporation Gemini Lake PCI Express Root Port (rev f3)
00:15.0 USB controller: Intel Corporation Celeron/Pentium Silver Processor USB 3.0 xHCI Controller (rev 03)
00:16.0 Signal processing controller: Intel Corporation Celeron/Pentium Silver Processor I2C 0 (rev 03)
00:16.1 Signal processing controller: Intel Corporation Celeron/Pentium Silver Processor I2C 1 (rev 03)
00:16.2 Signal processing controller: Intel Corporation Celeron/Pentium Silver Processor I2C 2 (rev 03)
00:16.3 Signal processing controller: Intel Corporation Celeron/Pentium Silver Processor I2C 3 (rev 03)
00:17.0 Signal processing controller: Intel Corporation Celeron/Pentium Silver Processor I2C 4 (rev 03)
00:17.1 Signal processing controller: Intel Corporation Celeron/Pentium Silver Processor I2C 5 (rev 03)
00:17.2 Signal processing controller: Intel Corporation Celeron/Pentium Silver Processor I2C 6 (rev 03)
00:17.3 Signal processing controller: Intel Corporation Celeron/Pentium Silver Processor I2C 7 (rev 03)
00:19.0 Signal processing controller: Intel Corporation Celeron/Pentium Silver Processor Serial IO SPI Host Controller (rev 03)
00:19.1 Signal processing controller: Intel Corporation Celeron/Pentium Silver Processor Serial IO SPI Host Controller (rev 03)
00:19.2 Signal processing controller: Intel Corporation Celeron/Pentium Silver Processor Serial IO SPI Host Controller (rev 03)
00:1f.0 ISA bridge: Intel Corporation Celeron/Pentium Silver Processor LPC Controller (rev 03)
00:1f.1 SMBus: Intel Corporation Celeron/Pentium Silver Processor Gaussian Mixture Model (rev 03)
01:00.0 Network controller: MEDIATEK Corp. Device 7906
02:00.0 Ethernet controller: Realtek Semiconductor Co., Ltd. RTL8125 2.5GbE Controller (rev 05)
03:00.0 Ethernet controller: Realtek Semiconductor Co., Ltd. RTL8111/8168/8211/8411 PCI Express Gigabit Ethernet Controller (rev 0c)
04:00.0 Non-Volatile memory controller: Samsung Electronics Co Ltd NVMe SSD Controller PM9B1 (DRAM-less) (rev 02)

szczegóły portu pcie ze złącza PoE:

el@akacja:~$ sudo lspci -s 04:00.0 -vvv
04:00.0 Non-Volatile memory controller: Samsung Electronics Co Ltd NVMe SSD Controller PM9B1 (DRAM-less) (rev 02) (prog-if 02 [NVM Express])
    Subsystem: Samsung Electronics Co Ltd NVMe SSD Controller PM9B1 (DRAM-less)
    Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx+
    Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
    Latency: 0, Cache Line Size: 64 bytes
    Interrupt: pin A routed to IRQ 21
    Region 0: Memory at a1300000 (64-bit, non-prefetchable) [size=16K]
    Capabilities: [40] Power Management version 3
        Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0+,D1-,D2-,D3hot+,D3cold-)
        Status: D0 NoSoftRst+ PME-Enable- DSel=0 DScale=0 PME-
    Capabilities: [70] Express (v2) Endpoint, IntMsgNum 0
        DevCap:    MaxPayload 512 bytes, PhantFunc 0, Latency L0s unlimited, L1 unlimited
            ExtTag- AttnBtn- AttnInd- PwrInd- RBE+ FLReset+ SlotPowerLimit 10W TEE-IO-
        DevCtl:    CorrErr- NonFatalErr- FatalErr- UnsupReq-
            RlxdOrd+ ExtTag- PhantFunc- AuxPwr- NoSnoop- FLReset-
            MaxPayload 256 bytes, MaxReadReq 256 bytes
        DevSta:    CorrErr- NonFatalErr- FatalErr- UnsupReq- AuxPwr- TransPend-
        LnkCap:    Port #0, Speed 16GT/s, Width x4, ASPM L1, Exit Latency L1 <64us
            ClockPM- Surprise- LLActRep- BwNot- ASPMOptComp+
        LnkCtl:    ASPM Disabled; RCB 64 bytes, LnkDisable- CommClk+
            ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt- FltModeDis-
        LnkSta:    Speed 5GT/s (downgraded), Width x1 (downgraded)
            TrErr- Train- SlotClk+ DLActive- BWMgmt- ABWMgmt-
        DevCap2: Completion Timeout: Range ABCD, TimeoutDis+ NROPrPrP- LTR+
             10BitTagComp+ 10BitTagReq- OBFF Not Supported, ExtFmt- EETLPPrefix-
             EmergencyPowerReduction Not Supported, EmergencyPowerReductionInit-
             FRS+ TPHComp- ExtTPHComp-
             AtomicOpsCap: 32bit- 64bit- 128bitCAS-
        DevCtl2: Completion Timeout: 50us to 50ms, TimeoutDis-
             AtomicOpsCtl: ReqEn-
             IDOReq- IDOCompl- LTR+ EmergencyPowerReductionReq-
             10BitTagReq- OBFF Disabled, EETLPPrefixBlk-
        LnkCap2: Supported Link Speeds: 2.5-16GT/s, Crosslink- Retimer+ 2Retimers+ DRS+
        LnkCtl2: Target Link Speed: 16GT/s, EnterCompliance- SpeedDis-
             Transmit Margin: Normal Operating Range, EnterModifiedCompliance- ComplianceSOS-
             Compliance Preset/De-emphasis: -6dB de-emphasis, 0dB preshoot
        LnkSta2: Current De-emphasis Level: -3.5dB, EqualizationComplete- EqualizationPhase1-
             EqualizationPhase2- EqualizationPhase3- LinkEqualizationRequest-
             Retimer- 2Retimers- CrosslinkRes: Upstream Port, FltMode-
    Capabilities: [b0] MSI-X: Enable+ Count=67 Masked-
        Vector table: BAR=0 offset=00002000
        PBA: BAR=0 offset=00003000
    Capabilities: [100 v2] Advanced Error Reporting
        UESta:    DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP-
            ECRC- UnsupReq- ACSViol- UncorrIntErr- BlockedTLP- AtomicOpBlocked- TLPBlockedErr-
            PoisonTLPBlocked- DMWrReqBlocked- IDECheck- MisIDETLP- PCRC_CHECK- TLPXlatBlocked-
        UEMsk:    DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP-
            ECRC- UnsupReq- ACSViol- UncorrIntErr+ BlockedTLP- AtomicOpBlocked- TLPBlockedErr-
            PoisonTLPBlocked- DMWrReqBlocked- IDECheck- MisIDETLP- PCRC_CHECK- TLPXlatBlocked-
        UESvrt:    DLP+ SDES+ TLP- FCP+ CmpltTO- CmpltAbrt- UnxCmplt- RxOF+ MalfTLP+
            ECRC- UnsupReq- ACSViol- UncorrIntErr+ BlockedTLP- AtomicOpBlocked- TLPBlockedErr-
            PoisonTLPBlocked- DMWrReqBlocked- IDECheck- MisIDETLP- PCRC_CHECK- TLPXlatBlocked-
        CESta:    RxErr- BadTLP- BadDLLP- Rollover- Timeout- AdvNonFatalErr- CorrIntErr- HeaderOF-
        CEMsk:    RxErr- BadTLP- BadDLLP- Rollover- Timeout- AdvNonFatalErr+ CorrIntErr+ HeaderOF+
        AERCap:    First Error Pointer: 00, ECRCGenCap+ ECRCGenEn+ ECRCChkCap+ ECRCChkEn+
            MultHdrRecCap- MultHdrRecEn- TLPPfxPres- HdrLogCap-
        HeaderLog: 00000000 00000000 00000000 00000000
    Capabilities: [148 v1] Device Serial Number 00-00-00-00-00-00-00-00
    Capabilities: [158 v1] Power Budgeting <?>
    Capabilities: [168 v1] Alternative Routing-ID Interpretation (ARI)
        ARICap:    MFVC- ACS-, Next Function: 0
        ARICtl:    MFVC- ACS-, Function Group: 0
    Capabilities: [178 v1] Secondary PCI Express
        LnkCtl3: LnkEquIntrruptEn- PerformEqu-
        LaneErrStat: 0
    Capabilities: [198 v1] Physical Layer 16.0 GT/s
        Phy16Sta: EquComplete- EquPhase1- EquPhase2- EquPhase3- LinkEquRequest-
    Capabilities: [1bc v1] Lane Margining at the Receiver
        PortCap: Uses Driver-
        PortSta: MargReady- MargSoftReady-
    Capabilities: [224 v1] Latency Tolerance Reporting
        Max snoop latency: 3145728ns
        Max no snoop latency: 3145728ns
    Capabilities: [22c v1] L1 PM Substates
        L1SubCap: PCI-PM_L1.2+ PCI-PM_L1.1+ ASPM_L1.2+ ASPM_L1.1+ L1_PM_Substates+
              PortCommonModeRestoreTime=10us PortTPowerOnTime=10us
        L1SubCtl1: PCI-PM_L1.2+ PCI-PM_L1.1+ ASPM_L1.2+ ASPM_L1.1+
               T_CommonMode=0us LTR1.2_Threshold=163840ns
        L1SubCtl2: T_PwrOn=10us
    Kernel driver in use: nvme
    Kernel modules: nvme

156 Odpowiedź przez Mieze

  • Mieze
  • Użytkownik
  • Nieaktywny
  • Zarejestrowany: 2026-06-09
  • Posty: 4

Odp: Router/firewall/NAS DIY na terminalu Fujitsu FUTRO S940. Czy się uda?

@Bern Thank you very much for the information!

I extracted the UEFI setup variables from V5.0.0.13 R1.14.0 for the D3543-A1x and documented my findings https://github.com/Mieze/Futro-S940-Inf … /tree/main just in case it might be helpful to anybody. The Repo also includes information how to enable ASPM for individual PCIe root ports.

157 Odpowiedź przez bern

  • bern
  • Użytkownik
  • Nieaktywny
  • Zarejestrowany: 2012-04-17
  • Posty: 134

Odp: Router/firewall/NAS DIY na terminalu Fujitsu FUTRO S940. Czy się uda?

Mieze napisał/a:

@Bern Thank you very much for the information!

I extracted the UEFI setup variables from V5.0.0.13 R1.14.0 for the D3543-A1x and documented my findings https://github.com/Mieze/Futro-S940-Inf … /tree/main just in case it might be helpful to anybody. The Repo also includes information how to enable ASPM for individual PCIe root ports.

@Mieze Thank you very much for extracting and documenting these UEFI setup variables. This is exactly the kind of information I was missing when I tried to optimize idle power consumption on my FutRO S940 about a year ago. The hardware clearly reported ASPM/L1 capability, but I could not find any ASPM option in the BIOS setup menu.

For reference, my unit reports:

el@akacja:~$ sudo inxi -M
Machine:
  Type: N/A System: FUJITSU product: D3543-A1 v: N/A serial: N/A
  Mobo: FUJITSU model: D3543-A1 v: S26361-D3543-A11 serial: N/A UEFI: FUJITSU
    // American Megatrends v: 5.0.0.13 R1.14.0 for D3543-A1x date: 11/20/2024

And lspci -tv shows the device connected via the former PoE connector as:
00:13.3-[04]----00.0 Samsung Electronics Co Ltd NVMe SSD Controller PM9B1
So on my machine the PoE connector appears to be routed to PCIe root port 00:13.3.

el@akacja:~$ lspci -tv
-[0000:00]-+-00.0  Intel Corporation Gemini Lake Host Bridge
           +-00.1  Intel Corporation Celeron/Pentium Silver Processor Dynamic Platform and Thermal Framework Processor Participant
           +-00.3  Intel Corporation Celeron/Pentium Silver Processor Gaussian Mixture Model
           +-02.0  Intel Corporation GeminiLake [UHD Graphics 605]
           +-0e.0  Intel Corporation Celeron/Pentium Silver Processor High Definition Audio
           +-0f.0  Intel Corporation Celeron/Pentium Silver Processor Trusted Execution Engine Interface
           +-12.0  Intel Corporation Celeron/Pentium Silver Processor SATA Controller
           +-13.0-[01]----00.0  MEDIATEK Corp. Device 7906
           +-13.1-[02]----00.0  Realtek Semiconductor Co., Ltd. RTL8125 2.5GbE Controller
           +-13.2-[03]----00.0  Realtek Semiconductor Co., Ltd. RTL8111/8168/8211/8411 PCI Express Gigabit Ethernet Controller
           +-13.3-[04]----00.0  Samsung Electronics Co Ltd NVMe SSD Controller PM9B1 (DRAM-less)
           +-14.0-[05]--
           +-14.1-[06]--
           +-15.0  Intel Corporation Celeron/Pentium Silver Processor USB 3.0 xHCI Controller
           +-16.0  Intel Corporation Celeron/Pentium Silver Processor I2C 0
           +-16.1  Intel Corporation Celeron/Pentium Silver Processor I2C 1
           +-16.2  Intel Corporation Celeron/Pentium Silver Processor I2C 2
           +-16.3  Intel Corporation Celeron/Pentium Silver Processor I2C 3
           +-17.0  Intel Corporation Celeron/Pentium Silver Processor I2C 4
           +-17.1  Intel Corporation Celeron/Pentium Silver Processor I2C 5
           +-17.2  Intel Corporation Celeron/Pentium Silver Processor I2C 6
           +-17.3  Intel Corporation Celeron/Pentium Silver Processor I2C 7
           +-19.0  Intel Corporation Celeron/Pentium Silver Processor Serial IO SPI Host Controller
           +-19.1  Intel Corporation Celeron/Pentium Silver Processor Serial IO SPI Host Controller
           +-19.2  Intel Corporation Celeron/Pentium Silver Processor Serial IO SPI Host Controller
           +-1f.0  Intel Corporation Celeron/Pentium Silver Processor LPC Controller
           \-1f.1  Intel Corporation Celeron/Pentium Silver Processor Gaussian Mixture Model

The NVMe device reports ASPM L1 and L1 PM substates capability, but LnkCtl still says ASPM Disabled, which fits perfectly with the missing/hidden BIOS-level ASPM setting.

I have not tried changing the UEFI variables yet, but if enabling Native ASPM and the corresponding root-port setting works, this would be very useful information for Futro S940 tinkerers and DIY users trying to reduce idle power consumption.

Thanks again for sharing this.

158 Odpowiedź przez Mieze

  • Mieze
  • Użytkownik
  • Nieaktywny
  • Zarejestrowany: 2026-06-09
  • Posty: 4

Odp: Router/firewall/NAS DIY na terminalu Fujitsu FUTRO S940. Czy się uda?

I've added output of lspci -vvv to the repository to show that ASPM is working for the RTL8111, the Wifi m.2 and a RTL8125A in the PCIex1 slot. As convenience I also added download links to Intel's website for the SoC's data sheets.

159 Odpowiedź przez bern (edytowany przez bern 2026-06-13 10:57:12)

  • bern
  • Użytkownik
  • Nieaktywny
  • Zarejestrowany: 2012-04-17
  • Posty: 134

Odp: Router/firewall/NAS DIY na terminalu Fujitsu FUTRO S940. Czy się uda?

Dzięki instrukcji @Mieze
https://github.com/Mieze/Futro-S940-Inf … nable-aspm
udało się odblokować i włączyć ASPM dla S940
Używając setup_var.efi wprowadziłem generalnie  zmienne Auto dla każdego portu:

setup_var.efi --reboot=auto --write_on_demand Setup:0x4E0=0x01 Setup:0x305=0x04 Setup:0x306=0x04 Setup:0x307=0x04 Setup:0x308=0x04

Poniżej wynik po reboocie:

ela@akacja:~$ echo "ASPM policy:"
cat /sys/module/pcie_aspm/parameters/policy
echo

check_link() {
  local name="$1"
  local root="$2"
  local dev="$3"

  echo
  echo "=============================="
  echo "$name"
  echo "Root port: $root"
  echo "Endpoint:  $dev"
  echo "=============================="

  echo
  echo "--- Root port $root ---"
  sudo lspci -s "$root" -vvv | grep -Ei \
    'LnkCap:|LnkCtl:|LnkSta:|L1SubCap:|L1SubCtl1:|L1SubCtl2:'

  echo
  echo "--- Endpoint $dev ---"
  sudo lspci -s "$dev" -vvv | grep -Ei \
    'LnkCap:|LnkCtl:|LnkSta:|L1SubCap:|L1SubCtl1:|L1SubCtl2:'
}

check_link "MediaTek Wi-Fi / PCIe x1 slot" "00:13.0" "01:00.0"
check_link "Realtek RTL8125 2.5G"       "00:13.1" "02:00.0"
check_link "Realtek RTL8111 onboard"    "00:13.2" "03:00.0"
check_link "NVMe on PoE connector"      "00:13.3" "04:00.0"
ASPM policy:
[default] performance powersave powersupersave 


==============================
MediaTek Wi-Fi / PCIe x1 slot
Root port: 00:13.0
Endpoint:  01:00.0
==============================

--- Root port 00:13.0 ---
        LnkCap:    Port #3, Speed 5GT/s, Width x1, ASPM L0s L1, Exit Latency L0s <1us, L1 <4us
        LnkCtl:    ASPM Disabled; RCB 64 bytes, LnkDisable- CommClk+
        LnkSta:    Speed 5GT/s, Width x1
        L1SubCap: PCI-PM_L1.2+ PCI-PM_L1.1+ ASPM_L1.2+ ASPM_L1.1+ L1_PM_Substates+
        L1SubCtl1: PCI-PM_L1.2+ PCI-PM_L1.1+ ASPM_L1.2+ ASPM_L1.1+
        L1SubCtl2: T_PwrOn=52us

--- Endpoint 01:00.0 ---
        LnkCap:    Port #1, Speed 5GT/s, Width x2, ASPM L0s L1, Exit Latency L0s <2us, L1 <8us
        LnkCtl:    ASPM Disabled; RCB 64 bytes, LnkDisable- CommClk+
        LnkSta:    Speed 5GT/s, Width x1 (downgraded)
        L1SubCap: PCI-PM_L1.2+ PCI-PM_L1.1+ ASPM_L1.2+ ASPM_L1.1+ L1_PM_Substates+
        L1SubCtl1: PCI-PM_L1.2+ PCI-PM_L1.1+ ASPM_L1.2+ ASPM_L1.1+
        L1SubCtl2: T_PwrOn=52us

==============================
Realtek RTL8125 2.5G
Root port: 00:13.1
Endpoint:  02:00.0
==============================

--- Root port 00:13.1 ---
        LnkCap:    Port #4, Speed 5GT/s, Width x1, ASPM L0s L1, Exit Latency L0s <1us, L1 <4us
        LnkCtl:    ASPM L1 Enabled; RCB 64 bytes, LnkDisable- CommClk+
        LnkSta:    Speed 5GT/s, Width x1
        L1SubCap: PCI-PM_L1.2+ PCI-PM_L1.1+ ASPM_L1.2+ ASPM_L1.1+ L1_PM_Substates+
        L1SubCtl1: PCI-PM_L1.2+ PCI-PM_L1.1+ ASPM_L1.2+ ASPM_L1.1+
        L1SubCtl2: T_PwrOn=150us

--- Endpoint 02:00.0 ---
pcilib: sysfs_read_vpd: read failed: No such device
        LnkCap:    Port #0, Speed 5GT/s, Width x1, ASPM L0s L1, Exit Latency L0s unlimited, L1 <64us
        LnkCtl:    ASPM L1 Enabled; RCB 64 bytes, LnkDisable- CommClk+
        LnkSta:    Speed 5GT/s, Width x1
        L1SubCap: PCI-PM_L1.2+ PCI-PM_L1.1+ ASPM_L1.2+ ASPM_L1.1+ L1_PM_Substates+
        L1SubCtl1: PCI-PM_L1.2+ PCI-PM_L1.1+ ASPM_L1.2+ ASPM_L1.1+
        L1SubCtl2: T_PwrOn=150us

==============================
Realtek RTL8111 onboard
Root port: 00:13.2
Endpoint:  03:00.0
==============================

--- Root port 00:13.2 ---
        LnkCap:    Port #5, Speed 5GT/s, Width x1, ASPM L0s L1, Exit Latency L0s <1us, L1 <4us
        LnkCtl:    ASPM L1 Enabled; RCB 64 bytes, LnkDisable- CommClk+
        LnkSta:    Speed 2.5GT/s, Width x1
        L1SubCap: PCI-PM_L1.2+ PCI-PM_L1.1+ ASPM_L1.2+ ASPM_L1.1+ L1_PM_Substates+
        L1SubCtl1: PCI-PM_L1.2- PCI-PM_L1.1- ASPM_L1.2- ASPM_L1.1-
        L1SubCtl2: T_PwrOn=10us

--- Endpoint 03:00.0 ---
pcilib: sysfs_read_vpd: read failed: No such device
        LnkCap:    Port #0, Speed 2.5GT/s, Width x1, ASPM L0s L1, Exit Latency L0s unlimited, L1 <64us
        LnkCtl:    ASPM L1 Enabled; RCB 64 bytes, LnkDisable- CommClk+
        LnkSta:    Speed 2.5GT/s, Width x1

==============================
NVMe on PoE connector
Root port: 00:13.3
Endpoint:  04:00.0
==============================

--- Root port 00:13.3 ---
        LnkCap:    Port #6, Speed 5GT/s, Width x1, ASPM L0s L1, Exit Latency L0s <1us, L1 <4us
        LnkCtl:    ASPM L1 Enabled; RCB 64 bytes, LnkDisable- CommClk+
        LnkSta:    Speed 5GT/s, Width x1
        L1SubCap: PCI-PM_L1.2+ PCI-PM_L1.1+ ASPM_L1.2+ ASPM_L1.1+ L1_PM_Substates+
        L1SubCtl1: PCI-PM_L1.2+ PCI-PM_L1.1+ ASPM_L1.2+ ASPM_L1.1+
        L1SubCtl2: T_PwrOn=10us

--- Endpoint 04:00.0 ---
        LnkCap:    Port #0, Speed 16GT/s, Width x4, ASPM L1, Exit Latency L1 <64us
        LnkCtl:    ASPM L1 Enabled; RCB 64 bytes, LnkDisable- CommClk+
        LnkSta:    Speed 5GT/s (downgraded), Width x1 (downgraded)
        L1SubCap: PCI-PM_L1.2+ PCI-PM_L1.1+ ASPM_L1.2+ ASPM_L1.1+ L1_PM_Substates+
        L1SubCtl1: PCI-PM_L1.2+ PCI-PM_L1.1+ ASPM_L1.2+ ASPM_L1.1+
        L1SubCtl2: T_PwrOn=10us

to, że dla karty 'MEDIATEK Corp. Device 7906' wyszło LnkCtl: ASPM Disabled to normalne bo ASPM jest zablokowany w sterowniku tej karty.
Dla starszego gigabitowego NIC
'Realtek Semiconductor Co., Ltd. RTL8111/8168/8211/8411 PCI Express Gigabit Ethernet'
L1.1/L1.2 jest wyłączone ale to starsza karta i nie obsługuje L1SS

Za to dla kart:
'Realtek Semiconductor Co., Ltd. RTL8125 2.5GbE Controller' oraz
'Samsung Electronics Co Ltd NVMe SSD Controller PM9B1'
ASPM L1:   włączone
L1.1/L1.2: włączone

160 Odpowiedź przez Adam1394

  • Zarejestrowany: 2024-04-09
  • Posty: 28

Odp: Router/firewall/NAS DIY na terminalu Fujitsu FUTRO S940. Czy się uda?

bern napisał/a:

Ja już nie używam FUTRO S940 bo przesiadłem się na ODROID H3+ ale wygrzebałem gdzieś z pudeł ten starszy sprzęt i odpaliłem.


Nie sprzedajesz może swojej przejściówki PoE -> M.2 ??   smile

161 Odpowiedź przez bern (edytowany przez bern 2026-06-30 11:21:07)

  • bern
  • Użytkownik
  • Nieaktywny
  • Zarejestrowany: 2012-04-17
  • Posty: 134

Odp: Router/firewall/NAS DIY na terminalu Fujitsu FUTRO S940. Czy się uda?

Adam1394 napisał/a:

Nie sprzedajesz może swojej przejściówki PoE -> M.2 ??   smile

Na razie nie bo trzymam Futro S940 (z modyfikacjami) jako sprzęt backupowy.

162 Odpowiedź przez Mieze (edytowany przez Mieze 2026-07-03 20:28:27)

  • Mieze
  • Użytkownik
  • Nieaktywny
  • Zarejestrowany: 2026-06-09
  • Posty: 4

Odp: Router/firewall/NAS DIY na terminalu Fujitsu FUTRO S940. Czy się uda?

Reading all the posts in this I realized that users tried to find a way to get more PCIe ports and I think that this idea is interesting Unfortunately, all attempts have failed so far, so that I decided to dig deeper and checked the data sheets (download links for them can be found in my GitHub repository I mention above). On page 96ff of volume 1 of the data sheet the architecture of the CPU's PCIe interface is described in detail.

The 6 lanes are organized as a PCIe x4 and a PCIe x2 port. Both of them can be bifurcated in a flexible way. 3 of the 6 lanes are dedicated to PCIe (lane 0-2 of the x4 port), the other are shared with the USB3 controller, see page 93 of vol. 1 of the datasheet, and must be configured statically as USB or PCIe ports by soft straps, which are part of the UEFI and are read from flash by the ME after power on, so that the port configuration can be changed by modifying the UEFI ROM. Unfortunately, not all of them can be changed easily. There are two regions in the UEFI, where soft straps can be found, in the flash descriptor (a 60 bytes region at offset 0x100 in the ROM), and in the SMIP (Signed Master Image Profile), which contains a copy of the soft straps from the flash descriptor, together with additional straps only present in the SMIP. The straps in the descriptor can be changed with a hex editor, because the copy in the SMIP has no effect, but the other ones require the UEFI ROM image to be decomposed and rebuild by an Intel tool named Flash Image Tool (FIT), which is confidential but leaked copies can be found in the Internet. smile

Although 6 lanes are available, only 4 PCIe ports can be enabled as there are only 4 RefClk# and ClockReq# signals, which can be freely distributed to the active ports, provided that they are properly configured in pairs. The diagram on page 93 of the datasheet shows that the two lanes of the PCIe x2 controller are shared with the USB XHCI and that the Futro 940's UEFI maps them both to ports 2 and 3 and the XHCI controller. These pins are connected to the 19 pin USB3 onboard header. As the external circuitry of a SuperSpeed USB port is quite much like that of a PCIe 2.0 port, there shouldn't be a problem using these ports as PCIe signals, provided they are properly mapped to the PCIe x2 controller. In fact, the only major difference between both ports are the ESD protection diodes, which are present in a USB3 port, but they should not be a problem for PCIe signals. Everything else is pretty much the same and this is the reason why miners use USB3 cables and connectors to connect external GPUs to PCIe x1 ports. Flashing a modified UEFI without OEM signature also requires a flash programming tool, a 1.8V adapter (the board has a 1.8V flash chip and trying to flash without the adapter would fry the chip), and a connector clip for the SOP8 package.

My plan is to use these 2 Flex I/O lines for PCIe in order to get a x2 port using the RefClk# and the Reset signals from the PoE port. Of course, this can't be used for PCIe anymore in such a scenario but trading in a PCIe x1 port for a PCIe x2 port seems to be a good deal. Part one of my project, the UEFi mod is completed, but the hardware part of soldering a connector cable still has to be managed. I'm going to post detailed instructions of the tools and steps required to extract, modify and flash the UEFi in the repository https://github.com/Mieze/Futro-S940-Information as soon as possible. For the time being I'm posting the output of lspci with my modified UEFI running Ubuntu 26 LTS as a prove of concept. Realize that device 00.14.0 is running in a x2 configuration and the 00.14.1 is deactivated because the lane is occupied by 00.14.0.

ubuntu@ubuntu:~/Desktop$ sudo lspci -tv
-[0000:00]-+-00.0  Intel Corporation Gemini Lake Host Bridge
           +-00.1  Intel Corporation Celeron/Pentium Silver Processor Dynamic Platform and Thermal Framework Processor Participant
           +-00.3  Intel Corporation Celeron/Pentium Silver Processor Gaussian Mixture Model
           +-02.0  Intel Corporation GeminiLake [UHD Graphics 605]
           +-0f.0  Intel Corporation Celeron/Pentium Silver Processor Trusted Execution Engine Interface
           +-12.0  Intel Corporation Celeron/Pentium Silver Processor SATA Controller
           +-13.0-[01]----00.0  Realtek Semiconductor Co., Ltd. RTL8125 2.5GbE Controller
           +-13.1-[02]----00.0  MEDIATEK Corp. MT7925 802.11be 160MHz 2x2 PCIe Wireless Network Adapter [Filogic 360]
           +-13.2-[03]----00.0  Realtek Semiconductor Co., Ltd. RTL8111/8168/8211/8411 PCI Express Gigabit Ethernet Controller
           +-13.3-[04]--
           +-14.0-[05]--
           +-15.0  Intel Corporation Celeron/Pentium Silver Processor USB 3.0 xHCI Controller
           +-16.0  Intel Corporation Celeron/Pentium Silver Processor I2C 0
           +-16.1  Intel Corporation Celeron/Pentium Silver Processor I2C 1
           +-16.2  Intel Corporation Celeron/Pentium Silver Processor I2C 2
           +-16.3  Intel Corporation Celeron/Pentium Silver Processor I2C 3
           +-17.0  Intel Corporation Celeron/Pentium Silver Processor I2C 4
           +-17.1  Intel Corporation Celeron/Pentium Silver Processor I2C 5
           +-17.2  Intel Corporation Celeron/Pentium Silver Processor I2C 6
           +-17.3  Intel Corporation Celeron/Pentium Silver Processor I2C 7
           +-19.0  Intel Corporation Celeron/Pentium Silver Processor Serial IO SPI Host Controller
           +-19.1  Intel Corporation Celeron/Pentium Silver Processor Serial IO SPI Host Controller
           +-19.2  Intel Corporation Celeron/Pentium Silver Processor Serial IO SPI Host Controller
           +-1f.0  Intel Corporation Celeron/Pentium Silver Processor LPC Controller
           \-1f.1  Intel Corporation Celeron/Pentium Silver Processor Gaussian Mixture Model
ubuntu@ubuntu:~/Desktop$ sudo lspci -vvv -s 00:13.0
00:13.0 PCI bridge: Intel Corporation Gemini Lake PCI Express Root Port (rev f3) (prog-if 00 [Normal decode])
    Subsystem: Fujitsu Technology Solutions Device 1240
    Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx+
    Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
    Latency: 0, Cache Line Size: 64 bytes
    Interrupt: pin A routed to IRQ 123
    IOMMU group: 4
    Bus: primary=00, secondary=01, subordinate=01, sec-latency=0
    I/O behind bridge: e000-efff [size=4K] [16-bit]
    Memory behind bridge: a1400000-a14fffff [size=1M] [32-bit]
    Prefetchable memory behind bridge: 00000000fff00000-00000000000fffff [disabled] [64-bit]
    Secondary status: 66MHz- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- <SERR- <PERR-
    BridgeCtl: Parity- SERR+ NoISA- VGA- VGA16+ MAbort- >Reset- FastB2B-
        PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn-
    Capabilities: [40] Express (v2) Root Port (Slot+), IntMsgNum 0
        DevCap:    MaxPayload 256 bytes, PhantFunc 0
            ExtTag- RBE+ TEE-IO-
        DevCtl:    CorrErr- NonFatalErr- FatalErr- UnsupReq-
            RlxdOrd- ExtTag- PhantFunc- AuxPwr- NoSnoop-
            MaxPayload 256 bytes, MaxReadReq 128 bytes
        DevSta:    CorrErr- NonFatalErr- FatalErr- UnsupReq- AuxPwr+ TransPend-
        LnkCap:    Port #3, Speed 5GT/s, Width x1, ASPM L0s L1, Exit Latency L0s <1us, L1 <4us
            ClockPM- Surprise- LLActRep+ BwNot+ ASPMOptComp+
        LnkCtl:    ASPM L1 Enabled; RCB 64 bytes, LnkDisable- CommClk+
            ExtSynch- ClockPM- AutWidDis- BWInt+ AutBWInt+ FltModeDis-
        LnkSta:    Speed 5GT/s, Width x1
            TrErr- Train- SlotClk+ DLActive+ BWMgmt- ABWMgmt-
        SltCap:    AttnBtn- PwrCtrl- MRL- AttnInd- PwrInd- HotPlug- Surprise-
            Slot #1, PowerLimit 10W; Interlock- NoCompl+
        SltCtl:    Enable: AttnBtn- PwrFlt- MRL- PresDet- CmdCplt- HPIrq- LinkChg-
            Control: AttnInd Unknown, PwrInd Unknown, Power- Interlock-
        SltSta:    Status: AttnBtn- PowerFlt- MRL- CmdCplt- PresDet+ Interlock-
            Changed: MRL- PresDet- LinkState+
        RootCap: CRSVisible-
        RootCtl: ErrCorrectable- ErrNon-Fatal- ErrFatal- PMEIntEna- CRSVisible-
        RootSta: PME ReqID 0000, PMEStatus- PMEPending-
        DevCap2: Completion Timeout: Range ABC, TimeoutDis+ NROPrPrP- LTR+
             10BitTagComp- 10BitTagReq- OBFF Not Supported, ExtFmt- EETLPPrefix-
             EmergencyPowerReduction Not Supported, EmergencyPowerReductionInit-
             FRS- LN System CLS Not Supported, TPHComp- ExtTPHComp- ARIFwd+
             AtomicOpsCap: Routing- 32bit- 64bit- 128bitCAS-
        DevCtl2: Completion Timeout: 50us to 50ms, TimeoutDis+ ARIFwd-
             AtomicOpsCtl: ReqEn- EgressBlck-
             IDOReq- IDOCompl- LTR+ EmergencyPowerReductionReq-
             10BitTagReq- OBFF Disabled, EETLPPrefixBlk-
        LnkCap2: Supported Link Speeds: 2.5-5GT/s, Crosslink- Retimer- 2Retimers- DRS-
        LnkCtl2: Target Link Speed: 5GT/s, EnterCompliance- SpeedDis-
             Transmit Margin: Normal Operating Range, EnterModifiedCompliance- ComplianceSOS-
             Compliance Preset/De-emphasis: -6dB de-emphasis, 0dB preshoot
        LnkSta2: Current De-emphasis Level: -6dB, EqualizationComplete- EqualizationPhase1-
             EqualizationPhase2- EqualizationPhase3- LinkEqualizationRequest-
             Retimer- 2Retimers- CrosslinkRes: unsupported, FltMode-
    Capabilities: [80] MSI: Enable+ Count=1/1 Maskable- 64bit-
        Address: fee00218  Data: 0000
    Capabilities: [90] Subsystem: Fujitsu Technology Solutions Device 1240
    Capabilities: [a0] Power Management version 3
        Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0+,D1-,D2-,D3hot+,D3cold+)
        Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME-
    Capabilities: [100 v0] Null
    Capabilities: [140 v1] Access Control Services
        ACSCap:    SrcValid+ TransBlk+ ReqRedir+ CmpltRedir+ UpstreamFwd- EgressCtrl- DirectTrans-
        ACSCtl:    SrcValid+ TransBlk- ReqRedir+ CmpltRedir+ UpstreamFwd- EgressCtrl- DirectTrans-
    Capabilities: [150 v0] Null
    Capabilities: [200 v1] L1 PM Substates
        L1SubCap: PCI-PM_L1.2+ PCI-PM_L1.1+ ASPM_L1.2+ ASPM_L1.1+ L1_PM_Substates+
              PortCommonModeRestoreTime=40us PortTPowerOnTime=10us
        L1SubCtl1: PCI-PM_L1.2+ PCI-PM_L1.1+ ASPM_L1.2+ ASPM_L1.1+
               T_CommonMode=150us LTR1.2_Threshold=306176ns
        L1SubCtl2: T_PwrOn=150us
    Kernel driver in use: pcieport
    Kernel modules: shpchp

ubuntu@ubuntu:~/Desktop$ sudo lspci -vvv -s 00:13.1
00:13.1 PCI bridge: Intel Corporation Gemini Lake PCI Express Root Port (rev f3) (prog-if 00 [Normal decode])
    Subsystem: Fujitsu Technology Solutions Device 1240
    Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx+
    Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
    Latency: 0, Cache Line Size: 64 bytes
    Interrupt: pin B routed to IRQ 124
    IOMMU group: 5
    Bus: primary=00, secondary=02, subordinate=02, sec-latency=0
    I/O behind bridge: f000-0fff [disabled] [16-bit]
    Memory behind bridge: a1000000-a12fffff [size=3M] [32-bit]
    Prefetchable memory behind bridge: 00000000fff00000-00000000000fffff [disabled] [64-bit]
    Secondary status: 66MHz- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- <SERR- <PERR-
    BridgeCtl: Parity- SERR+ NoISA- VGA- VGA16+ MAbort- >Reset- FastB2B-
        PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn-
    Capabilities: [40] Express (v2) Root Port (Slot+), IntMsgNum 0
        DevCap:    MaxPayload 256 bytes, PhantFunc 0
            ExtTag- RBE+ TEE-IO-
        DevCtl:    CorrErr- NonFatalErr- FatalErr- UnsupReq-
            RlxdOrd- ExtTag- PhantFunc- AuxPwr- NoSnoop-
            MaxPayload 256 bytes, MaxReadReq 128 bytes
        DevSta:    CorrErr- NonFatalErr- FatalErr- UnsupReq- AuxPwr+ TransPend-
        LnkCap:    Port #4, Speed 5GT/s, Width x1, ASPM L0s L1, Exit Latency L0s <1us, L1 <4us
            ClockPM- Surprise- LLActRep+ BwNot+ ASPMOptComp+
        LnkCtl:    ASPM L0s L1 Enabled; RCB 64 bytes, LnkDisable- CommClk+
            ExtSynch- ClockPM- AutWidDis- BWInt+ AutBWInt+ FltModeDis-
        LnkSta:    Speed 5GT/s, Width x1
            TrErr- Train- SlotClk+ DLActive+ BWMgmt- ABWMgmt-
        SltCap:    AttnBtn- PwrCtrl- MRL- AttnInd- PwrInd- HotPlug- Surprise-
            Slot #2, PowerLimit 10W; Interlock- NoCompl+
        SltCtl:    Enable: AttnBtn- PwrFlt- MRL- PresDet- CmdCplt- HPIrq- LinkChg-
            Control: AttnInd Unknown, PwrInd Unknown, Power- Interlock-
        SltSta:    Status: AttnBtn- PowerFlt- MRL- CmdCplt- PresDet+ Interlock-
            Changed: MRL- PresDet- LinkState+
        RootCap: CRSVisible-
        RootCtl: ErrCorrectable- ErrNon-Fatal- ErrFatal- PMEIntEna- CRSVisible-
        RootSta: PME ReqID 0000, PMEStatus- PMEPending-
        DevCap2: Completion Timeout: Range ABC, TimeoutDis+ NROPrPrP- LTR+
             10BitTagComp- 10BitTagReq- OBFF Not Supported, ExtFmt- EETLPPrefix-
             EmergencyPowerReduction Not Supported, EmergencyPowerReductionInit-
             FRS- LN System CLS Not Supported, TPHComp- ExtTPHComp- ARIFwd+
             AtomicOpsCap: Routing- 32bit- 64bit- 128bitCAS-
        DevCtl2: Completion Timeout: 50us to 50ms, TimeoutDis+ ARIFwd-
             AtomicOpsCtl: ReqEn- EgressBlck-
             IDOReq- IDOCompl- LTR+ EmergencyPowerReductionReq-
             10BitTagReq- OBFF Disabled, EETLPPrefixBlk-
        LnkCap2: Supported Link Speeds: 2.5-5GT/s, Crosslink- Retimer- 2Retimers- DRS-
        LnkCtl2: Target Link Speed: 5GT/s, EnterCompliance- SpeedDis-
             Transmit Margin: Normal Operating Range, EnterModifiedCompliance- ComplianceSOS-
             Compliance Preset/De-emphasis: -6dB de-emphasis, 0dB preshoot
        LnkSta2: Current De-emphasis Level: -6dB, EqualizationComplete- EqualizationPhase1-
             EqualizationPhase2- EqualizationPhase3- LinkEqualizationRequest-
             Retimer- 2Retimers- CrosslinkRes: unsupported, FltMode-
    Capabilities: [80] MSI: Enable+ Count=1/1 Maskable- 64bit-
        Address: fee00238  Data: 0000
    Capabilities: [90] Subsystem: Fujitsu Technology Solutions Device 1240
    Capabilities: [a0] Power Management version 3
        Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0+,D1-,D2-,D3hot+,D3cold+)
        Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME-
    Capabilities: [100 v0] Null
    Capabilities: [140 v1] Access Control Services
        ACSCap:    SrcValid+ TransBlk+ ReqRedir+ CmpltRedir+ UpstreamFwd- EgressCtrl- DirectTrans-
        ACSCtl:    SrcValid+ TransBlk- ReqRedir+ CmpltRedir+ UpstreamFwd- EgressCtrl- DirectTrans-
    Capabilities: [150 v0] Null
    Capabilities: [200 v1] L1 PM Substates
        L1SubCap: PCI-PM_L1.2+ PCI-PM_L1.1+ ASPM_L1.2+ ASPM_L1.1+ L1_PM_Substates+
              PortCommonModeRestoreTime=40us PortTPowerOnTime=10us
        L1SubCtl1: PCI-PM_L1.2+ PCI-PM_L1.1+ ASPM_L1.2+ ASPM_L1.1+
               T_CommonMode=40us LTR1.2_Threshold=98304ns
        L1SubCtl2: T_PwrOn=52us
    Kernel driver in use: pcieport
    Kernel modules: shpchp

ubuntu@ubuntu:~/Desktop$ sudo lspci -vvv -s 00:13.2
00:13.2 PCI bridge: Intel Corporation Gemini Lake PCI Express Root Port (rev f3) (prog-if 00 [Normal decode])
    Subsystem: Fujitsu Technology Solutions Device 1240
    Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx+
    Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
    Latency: 0, Cache Line Size: 64 bytes
    Interrupt: pin C routed to IRQ 125
    IOMMU group: 6
    Bus: primary=00, secondary=03, subordinate=03, sec-latency=0
    I/O behind bridge: d000-dfff [size=4K] [16-bit]
    Memory behind bridge: a1300000-a13fffff [size=1M] [32-bit]
    Prefetchable memory behind bridge: 00000000fff00000-00000000000fffff [disabled] [64-bit]
    Secondary status: 66MHz- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- <SERR- <PERR-
    BridgeCtl: Parity- SERR+ NoISA- VGA- VGA16+ MAbort- >Reset- FastB2B-
        PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn-
    Capabilities: [40] Express (v2) Root Port (Slot+), IntMsgNum 0
        DevCap:    MaxPayload 256 bytes, PhantFunc 0
            ExtTag- RBE+ TEE-IO-
        DevCtl:    CorrErr- NonFatalErr- FatalErr- UnsupReq-
            RlxdOrd- ExtTag- PhantFunc- AuxPwr- NoSnoop-
            MaxPayload 128 bytes, MaxReadReq 128 bytes
        DevSta:    CorrErr- NonFatalErr- FatalErr- UnsupReq- AuxPwr+ TransPend-
        LnkCap:    Port #5, Speed 5GT/s, Width x1, ASPM L0s L1, Exit Latency L0s <1us, L1 <4us
            ClockPM- Surprise- LLActRep+ BwNot+ ASPMOptComp+
        LnkCtl:    ASPM L1 Enabled; RCB 64 bytes, LnkDisable- CommClk+
            ExtSynch- ClockPM- AutWidDis- BWInt+ AutBWInt+ FltModeDis-
        LnkSta:    Speed 2.5GT/s, Width x1
            TrErr- Train- SlotClk+ DLActive+ BWMgmt- ABWMgmt-
        SltCap:    AttnBtn- PwrCtrl- MRL- AttnInd- PwrInd- HotPlug- Surprise-
            Slot #0, PowerLimit 10W; Interlock- NoCompl+
        SltCtl:    Enable: AttnBtn- PwrFlt- MRL- PresDet- CmdCplt- HPIrq- LinkChg-
            Control: AttnInd Unknown, PwrInd Unknown, Power- Interlock-
        SltSta:    Status: AttnBtn- PowerFlt- MRL- CmdCplt- PresDet+ Interlock-
            Changed: MRL- PresDet- LinkState+
        RootCap: CRSVisible-
        RootCtl: ErrCorrectable- ErrNon-Fatal- ErrFatal- PMEIntEna- CRSVisible-
        RootSta: PME ReqID 0000, PMEStatus- PMEPending-
        DevCap2: Completion Timeout: Range ABC, TimeoutDis+ NROPrPrP- LTR+
             10BitTagComp- 10BitTagReq- OBFF Not Supported, ExtFmt- EETLPPrefix-
             EmergencyPowerReduction Not Supported, EmergencyPowerReductionInit-
             FRS- LN System CLS Not Supported, TPHComp- ExtTPHComp- ARIFwd+
             AtomicOpsCap: Routing- 32bit- 64bit- 128bitCAS-
        DevCtl2: Completion Timeout: 50us to 50ms, TimeoutDis+ ARIFwd-
             AtomicOpsCtl: ReqEn- EgressBlck-
             IDOReq- IDOCompl- LTR+ EmergencyPowerReductionReq-
             10BitTagReq- OBFF Disabled, EETLPPrefixBlk-
        LnkCap2: Supported Link Speeds: 2.5-5GT/s, Crosslink- Retimer- 2Retimers- DRS-
        LnkCtl2: Target Link Speed: 5GT/s, EnterCompliance- SpeedDis-
             Transmit Margin: Normal Operating Range, EnterModifiedCompliance- ComplianceSOS-
             Compliance Preset/De-emphasis: -6dB de-emphasis, 0dB preshoot
        LnkSta2: Current De-emphasis Level: -3.5dB, EqualizationComplete- EqualizationPhase1-
             EqualizationPhase2- EqualizationPhase3- LinkEqualizationRequest-
             Retimer- 2Retimers- CrosslinkRes: unsupported, FltMode-
    Capabilities: [80] MSI: Enable+ Count=1/1 Maskable- 64bit-
        Address: fee00258  Data: 0000
    Capabilities: [90] Subsystem: Fujitsu Technology Solutions Device 1240
    Capabilities: [a0] Power Management version 3
        Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0+,D1-,D2-,D3hot+,D3cold+)
        Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME-
    Capabilities: [100 v0] Null
    Capabilities: [140 v1] Access Control Services
        ACSCap:    SrcValid+ TransBlk+ ReqRedir+ CmpltRedir+ UpstreamFwd- EgressCtrl- DirectTrans-
        ACSCtl:    SrcValid+ TransBlk- ReqRedir+ CmpltRedir+ UpstreamFwd- EgressCtrl- DirectTrans-
    Capabilities: [150 v0] Null
    Capabilities: [200 v1] L1 PM Substates
        L1SubCap: PCI-PM_L1.2+ PCI-PM_L1.1+ ASPM_L1.2+ ASPM_L1.1+ L1_PM_Substates+
              PortCommonModeRestoreTime=40us PortTPowerOnTime=10us
        L1SubCtl1: PCI-PM_L1.2- PCI-PM_L1.1- ASPM_L1.2- ASPM_L1.1-
               T_CommonMode=0us LTR1.2_Threshold=0ns
        L1SubCtl2: T_PwrOn=10us
    Kernel driver in use: pcieport
    Kernel modules: shpchp

ubuntu@ubuntu:~/Desktop$ sudo lspci -vvv -s 00:13.3
00:13.3 PCI bridge: Intel Corporation Gemini Lake PCI Express Root Port (rev f3) (prog-if 00 [Normal decode])
    Subsystem: Fujitsu Technology Solutions Device 1240
    Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx+
    Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
    Latency: 0, Cache Line Size: 64 bytes
    Interrupt: pin D routed to IRQ 126
    IOMMU group: 7
    Bus: primary=00, secondary=04, subordinate=04, sec-latency=0
    I/O behind bridge: f000-0fff [disabled] [16-bit]
    Memory behind bridge: fff00000-000fffff [disabled] [32-bit]
    Prefetchable memory behind bridge: 00000000fff00000-00000000000fffff [disabled] [64-bit]
    Secondary status: 66MHz- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- <SERR- <PERR-
    BridgeCtl: Parity- SERR+ NoISA- VGA- VGA16+ MAbort- >Reset- FastB2B-
        PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn-
    Capabilities: [40] Express (v2) Root Port (Slot+), IntMsgNum 0
        DevCap:    MaxPayload 256 bytes, PhantFunc 0
            ExtTag- RBE+ TEE-IO-
        DevCtl:    CorrErr- NonFatalErr- FatalErr- UnsupReq-
            RlxdOrd- ExtTag- PhantFunc- AuxPwr- NoSnoop-
            MaxPayload 256 bytes, MaxReadReq 128 bytes
        DevSta:    CorrErr- NonFatalErr- FatalErr- UnsupReq- AuxPwr+ TransPend-
        LnkCap:    Port #6, Speed 5GT/s, Width x1, ASPM L0s, Exit Latency L0s <1us
            ClockPM- Surprise- LLActRep+ BwNot+ ASPMOptComp+
        LnkCtl:    ASPM L0s Enabled; RCB 64 bytes, LnkDisable- CommClk-
            ExtSynch- ClockPM- AutWidDis- BWInt+ AutBWInt+ FltModeDis-
        LnkSta:    Speed 2.5GT/s, Width x0
            TrErr- Train+ SlotClk+ DLActive- BWMgmt- ABWMgmt-
        SltCap:    AttnBtn- PwrCtrl- MRL- AttnInd- PwrInd- HotPlug- Surprise-
            Slot #3, PowerLimit 10W; Interlock- NoCompl+
        SltCtl:    Enable: AttnBtn- PwrFlt- MRL- PresDet- CmdCplt- HPIrq- LinkChg-
            Control: AttnInd Unknown, PwrInd Unknown, Power- Interlock-
        SltSta:    Status: AttnBtn- PowerFlt- MRL- CmdCplt- PresDet- Interlock-
            Changed: MRL- PresDet- LinkState-
        RootCap: CRSVisible-
        RootCtl: ErrCorrectable- ErrNon-Fatal- ErrFatal- PMEIntEna- CRSVisible-
        RootSta: PME ReqID 0000, PMEStatus- PMEPending-
        DevCap2: Completion Timeout: Range ABC, TimeoutDis+ NROPrPrP- LTR+
             10BitTagComp- 10BitTagReq- OBFF Not Supported, ExtFmt- EETLPPrefix-
             EmergencyPowerReduction Not Supported, EmergencyPowerReductionInit-
             FRS- LN System CLS Not Supported, TPHComp- ExtTPHComp- ARIFwd+
             AtomicOpsCap: Routing- 32bit- 64bit- 128bitCAS-
        DevCtl2: Completion Timeout: 50us to 50ms, TimeoutDis+ ARIFwd-
             AtomicOpsCtl: ReqEn- EgressBlck-
             IDOReq- IDOCompl- LTR+ EmergencyPowerReductionReq-
             10BitTagReq- OBFF Disabled, EETLPPrefixBlk-
        LnkCap2: Supported Link Speeds: 2.5-5GT/s, Crosslink- Retimer- 2Retimers- DRS-
        LnkCtl2: Target Link Speed: 2.5GT/s, EnterCompliance- SpeedDis-
             Transmit Margin: Normal Operating Range, EnterModifiedCompliance- ComplianceSOS-
             Compliance Preset/De-emphasis: -6dB de-emphasis, 0dB preshoot
        LnkSta2: Current De-emphasis Level: -3.5dB, EqualizationComplete- EqualizationPhase1-
             EqualizationPhase2- EqualizationPhase3- LinkEqualizationRequest-
             Retimer- 2Retimers- CrosslinkRes: unsupported, FltMode-
    Capabilities: [80] MSI: Enable+ Count=1/1 Maskable- 64bit-
        Address: fee00278  Data: 0000
    Capabilities: [90] Subsystem: Fujitsu Technology Solutions Device 1240
    Capabilities: [a0] Power Management version 3
        Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0+,D1-,D2-,D3hot+,D3cold+)
        Status: D3 NoSoftRst- PME-Enable+ DSel=0 DScale=0 PME-
    Capabilities: [100 v0] Null
    Capabilities: [140 v1] Access Control Services
        ACSCap:    SrcValid+ TransBlk+ ReqRedir+ CmpltRedir+ UpstreamFwd- EgressCtrl- DirectTrans-
        ACSCtl:    SrcValid+ TransBlk- ReqRedir+ CmpltRedir+ UpstreamFwd- EgressCtrl- DirectTrans-
    Capabilities: [150 v0] Null
    Capabilities: [200 v1] L1 PM Substates
        L1SubCap: PCI-PM_L1.2+ PCI-PM_L1.1+ ASPM_L1.2+ ASPM_L1.1+ L1_PM_Substates+
              PortCommonModeRestoreTime=40us PortTPowerOnTime=10us
        L1SubCtl1: PCI-PM_L1.2- PCI-PM_L1.1- ASPM_L1.2- ASPM_L1.1-
               T_CommonMode=0us LTR1.2_Threshold=0ns
        L1SubCtl2: T_PwrOn=10us
    Kernel driver in use: pcieport
    Kernel modules: shpchp

ubuntu@ubuntu:~/Desktop$ sudo lspci -vvv -s 00:14.0
00:14.0 PCI bridge: Intel Corporation Gemini Lake PCI Express Root Port (rev f3) (prog-if 00 [Normal decode])
    Subsystem: Fujitsu Technology Solutions Device 1240
    Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx+
    Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
    Latency: 0, Cache Line Size: 64 bytes
    Interrupt: pin A routed to IRQ 127
    IOMMU group: 8
    Bus: primary=00, secondary=05, subordinate=05, sec-latency=0
    I/O behind bridge: f000-0fff [disabled] [16-bit]
    Memory behind bridge: fff00000-000fffff [disabled] [32-bit]
    Prefetchable memory behind bridge: 00000000fff00000-00000000000fffff [disabled] [64-bit]
    Secondary status: 66MHz- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- <SERR- <PERR-
    BridgeCtl: Parity- SERR+ NoISA- VGA- VGA16+ MAbort- >Reset- FastB2B-
        PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn-
    Capabilities: [40] Express (v2) Root Port (Slot+), IntMsgNum 0
        DevCap:    MaxPayload 256 bytes, PhantFunc 0
            ExtTag- RBE+ TEE-IO-
        DevCtl:    CorrErr- NonFatalErr- FatalErr- UnsupReq-
            RlxdOrd- ExtTag- PhantFunc- AuxPwr- NoSnoop-
            MaxPayload 256 bytes, MaxReadReq 128 bytes
        DevSta:    CorrErr- NonFatalErr- FatalErr- UnsupReq- AuxPwr+ TransPend-
        LnkCap:    Port #1, Speed 5GT/s, Width x2, ASPM not supported
            ClockPM- Surprise- LLActRep+ BwNot+ ASPMOptComp+
        LnkCtl:    ASPM Disabled; RCB 64 bytes, LnkDisable- CommClk-
            ExtSynch- ClockPM- AutWidDis- BWInt+ AutBWInt+ FltModeDis-
        LnkSta:    Speed 2.5GT/s, Width x0
            TrErr- Train- SlotClk+ DLActive- BWMgmt- ABWMgmt-
        SltCap:    AttnBtn- PwrCtrl- MRL- AttnInd- PwrInd- HotPlug- Surprise-
            Slot #0, PowerLimit 25W; Interlock- NoCompl+
        SltCtl:    Enable: AttnBtn- PwrFlt- MRL- PresDet- CmdCplt- HPIrq- LinkChg-
            Control: AttnInd Unknown, PwrInd Unknown, Power- Interlock-
        SltSta:    Status: AttnBtn- PowerFlt- MRL- CmdCplt- PresDet- Interlock-
            Changed: MRL- PresDet- LinkState-
        RootCap: CRSVisible-
        RootCtl: ErrCorrectable- ErrNon-Fatal- ErrFatal- PMEIntEna- CRSVisible-
        RootSta: PME ReqID 0000, PMEStatus- PMEPending-
        DevCap2: Completion Timeout: Range ABC, TimeoutDis+ NROPrPrP- LTR+
             10BitTagComp- 10BitTagReq- OBFF Not Supported, ExtFmt- EETLPPrefix-
             EmergencyPowerReduction Not Supported, EmergencyPowerReductionInit-
             FRS- LN System CLS Not Supported, TPHComp- ExtTPHComp- ARIFwd+
             AtomicOpsCap: Routing- 32bit- 64bit- 128bitCAS-
        DevCtl2: Completion Timeout: 50us to 50ms, TimeoutDis+ ARIFwd-
             AtomicOpsCtl: ReqEn- EgressBlck-
             IDOReq- IDOCompl- LTR- EmergencyPowerReductionReq-
             10BitTagReq- OBFF Disabled, EETLPPrefixBlk-
        LnkCap2: Supported Link Speeds: 2.5-5GT/s, Crosslink- Retimer- 2Retimers- DRS-
        LnkCtl2: Target Link Speed: 2.5GT/s, EnterCompliance- SpeedDis-
             Transmit Margin: Normal Operating Range, EnterModifiedCompliance- ComplianceSOS-
             Compliance Preset/De-emphasis: -6dB de-emphasis, 0dB preshoot
        LnkSta2: Current De-emphasis Level: -3.5dB, EqualizationComplete- EqualizationPhase1-
             EqualizationPhase2- EqualizationPhase3- LinkEqualizationRequest-
             Retimer- 2Retimers- CrosslinkRes: unsupported, FltMode-
    Capabilities: [80] MSI: Enable+ Count=1/1 Maskable- 64bit-
        Address: fee002b8  Data: 0000
    Capabilities: [90] Subsystem: Fujitsu Technology Solutions Device 1240
    Capabilities: [a0] Power Management version 3
        Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0+,D1-,D2-,D3hot+,D3cold+)
        Status: D3 NoSoftRst- PME-Enable+ DSel=0 DScale=0 PME-
    Capabilities: [100 v0] Null
    Capabilities: [140 v1] Access Control Services
        ACSCap:    SrcValid+ TransBlk+ ReqRedir+ CmpltRedir+ UpstreamFwd- EgressCtrl- DirectTrans-
        ACSCtl:    SrcValid+ TransBlk- ReqRedir+ CmpltRedir+ UpstreamFwd- EgressCtrl- DirectTrans-
    Capabilities: [150 v0] Null
    Capabilities: [200 v1] L1 PM Substates
        L1SubCap: PCI-PM_L1.2+ PCI-PM_L1.1+ ASPM_L1.2+ ASPM_L1.1+ L1_PM_Substates+
              PortCommonModeRestoreTime=40us PortTPowerOnTime=10us
        L1SubCtl1: PCI-PM_L1.2- PCI-PM_L1.1- ASPM_L1.2- ASPM_L1.1-
               T_CommonMode=0us LTR1.2_Threshold=0ns
        L1SubCtl2: T_PwrOn=10us
    Kernel driver in use: pcieport
    Kernel modules: shpchp

163 Odpowiedź przez bern

  • bern
  • Użytkownik
  • Nieaktywny
  • Zarejestrowany: 2012-04-17
  • Posty: 134

Odp: Router/firewall/NAS DIY na terminalu Fujitsu FUTRO S940. Czy się uda?

That is a very interesting idea and probably the most promising approach so far.

If I understand it correctly, the firmware side already looks like a successful proof of concept: the Flex I/O lanes formerly assigned to USB3 are now exposed as a PCIe x2 root port, while the remaining challenge is the hardware side — routing the two SuperSpeed pairs from the internal USB3 header as PCIe lanes and borrowing the required REFCLK and PERST# signals from the PoE header.

This is definitely more complex than just using the PoE connector as a single PCIe x1 port, but trading one x1 port for a potential Gen2 x2 link sounds like a very good deal, especially for NVMe or faster network adapters.

I am looking forward to your hardware experiments. If you manage to confirm whether CLKREQ# is also routed to the PoE header, that would be extremely valuable, because it would help to understand whether proper L1 substates can be used with devices attached through that connector.