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eko.one.pl → Posty przez ArTu
Coś temat ucichł....
To może ktoś by spróbował przełączyć modem w USB , sprawdził ,czy jest USB3.0 (w zewnętrznej przejściówce , bo może okaże się ,ze w gnieździe m.2. routera jest tylko 2.0 ) ?
Niestety ja nie pomogę bo nie posiadam przejściówki
Ale w m.2 USB jest ? I czy 3.0?
Może tam na płycie jest miejsce na chip huba ,ale go nie ma i ścieżki z Procka są zmostkowane i idą na m.2 tylko ….
https://drive.google.com/file/d/1cw_1nd … drive_link
Link do fotek niestety ścieżki nie idą po zewnętrznych stronach płytki na tyle co widzę ale też kable troche przeszkadzają
IceG napisał/a:Cezary napisał/a:Poszło mejlem. Działaj, bo i tak jak będzie wsparcie to ktoś to musi zgłosić do openwrt a ja sprzęt oddam prędzej zapewne niż dołożą wsparcie i nie będę w stanie odpowiadać na jakieś dziwne pytania "a jak tam w oryginalnym sofie jest coś zrobione" przy zgłoszeniach.
Cezary nie oddawaj jeeeszcze sprzętu. Nie rób Nam tego
.
Chcę tylko dodać iż na oczy nie widziałem oryginalnego softu na ten router, a to co obecnie działa to jest twór/ulep, mix rozwiązań nie do powtórzenia w podstawowym OpenWrt.
To jest oryginalny plik oprogramowania sprzętowego, który można zapisać bezpośrednio poprzez U-boot.
https://drive.google.com/drive/folders/ … drive_link
Oryginalne oprogramowanie układowe uruchamia się stosunkowo wolno (około 4 minut). Hasło znajduje się pod etykietą na spodzie (należy usunąć górną warstwę).openwrt Repozytorium kodu źródłowego pochodzi od niego(Ponieważ zawiera sterownik NSS)lede
https://github.com/coolsnowwolf
No muszę przyznać że nieźle wykopane z odmętów Internetu ;p
ArTu napisał/a:Gdyby jeszcze była opcja zintegrowania w sofcie obsługi Wireguarda byłbym mega wdzięczny bo to jedyne czego mi brakuje w oryginalnym sofcie
Jeżeli będzie wsparcie zrobione to sobie zainstalujesz co będziesz chciał.
Było by super
ArTu napisał/a:z ciekawości jeszcze podpytam na jakim sprzęcie kompilujesz?
Zwykły laptop z Ryzenem 7
ile trwa u ciebie kompilacja? te próby co robiłem korzystałem z m1 to średnio koło 50min i zastanawiam się jak to czasowo wychodziło
Jeszcze raz napiszę - kompletnie nie masz doświadczenia z tą architekturą, więc niektóre rzeczy robione są na podstawie innych urządzeń i nawet się nie zastanawiam dlaczego jest tak a nie inaczej zrobione. Poniżej stan moich prac na dzień edycji tego postu:
Działa i sprawdzone
- wczytywanie obrazu przez tftp
- uruchamianie obrazu w ramie
- obsługa lanów jako DSA
- obsługa wanu
- obsługa przycisków
- obsługa ledów
- wykorzystanie jednego z ledów do sygnalizowania startu
- obsługa usb
- obsługa modemu (przynajmniej jako proto 3g)Do sprawdzenia
- przypisanie adresów mac do interfejsów tak jak było w oryginalnym sofcie
- obsługa wifi (coś tam się próbuje uruchamiać ale wykłada się na braku firmware, do sprawdzenia które i jaki trzeba mu dać)
- co z modemem i jego jego obsługą na MHI
- czemu modem nie ma qmi/mbim i czy trzeba go przełączyć w inny tryb (na razie tego nie robiłem bo wracam co chwilę do oryginału żeby sprawdzić czy i jak coś działa, jak go przełączę to nie chcę później pod oryginalnym się bawić w kolejne przełączanie żeby oryginał obsługiwał go "po staremu")
- zewnętrzne USB
- recovery przez gui
- przywracanie oryginalnego softuNie sprawdzone/nie zrobione
- sysupgrade
- zapisywanie obrazu do flash
- wydajność systemuLista będzie się zmieniać i aktualizować w miarę postępu pracy (ale to już idzie swoim tempem).
FAQ:
- Czy uda się zrobić dla niego wsparcie: pewnie tak.
- Kiedy uda się zrobić dla niego pełne wsparcie: w miarę wolnego czasu. Nikt mnie jeszcze nie pogania w tej sprawie aczkolwiek należało by oddać sprzęt w jakim sensowym czasie i dobrze by było żeby to nie był rok.
- Czy będą obrazy normalnie dostępne: trudno powiedzieć. W wydaniu stabilnym w ogóle nie ma obsługi tej architektury, wszystkie prace dotyczą wersji rozwojowej OpenWrt. Więc wprawcie - o ile powstanie - będzie tylko w wersji rozwojowej, chyba że do czasu ukończenia prac zdąży się już utworzyć nowe wydanie stabilne
Kurczę jednak jak ktoś wie co robi to idzie znacznie lepiej jak trzeba coś potestować mogę wrzucić na swojego i sprawdzać w teorii mam zgrany cały nand wiec brick nie powinien być straszy chyba że ubije uboota chociaż jak sie domyślam można te pliki połączyć w jedną binarkę i wrzucić programatorem bezpośrednio do nandu. Gdyby jeszcze była opcja zintegrowania w sofcie obsługi Wireguarda byłbym mega wdzięczny bo to jedyne czego mi brakuje w oryginalnym sofcie z ciekawości jeszcze podpytam na jakim sprzęcie kompilujesz?
No też nie masz
root@Exigo_Hub:/dev# ls -l
drwxr-xr-x 3 root root 60 Nov 30 14:07 bus
crw------- 1 root root 5, 1 Dec 2 17:29 console
crw------- 1 root root 239, 0 Jan 1 1970 coresight-stm
crw------- 1 root root 10, 61 Jan 1 1970 coresight-tmc-etf
crw------- 1 root root 10, 62 Jan 1 1970 coresight-tmc-etr
crw------- 1 root root 10, 63 Jan 1 1970 cpu_dma_latency
crw------- 1 root root 10, 59 Nov 30 14:07 crypto
crw------- 1 root root 236, 0 Nov 30 14:07 diag
lrwxrwxrwx 1 root root 13 Jan 1 1970 fd -> /proc/self/fd
crw-rw-rw- 1 root root 1, 7 Jan 1 1970 full
crw------- 1 root root 10, 229 Nov 30 14:07 fuse
crw------- 1 root root 254, 0 Jan 1 1970 gpiochip0
crw------- 1 root root 10, 183 Jan 1 1970 hwrng
crw------- 1 root root 1, 11 Jan 1 1970 kmsg
-rw-r--r-- 1 root root 25 Nov 30 14:07 ksmg
srw-rw-rw- 1 root root 0 Nov 30 14:07 log
crw------- 1 root root 10, 237 Jan 1 1970 loop-control
brw------- 1 root root 7, 0 Jan 1 1970 loop0
brw------- 1 root root 7, 1 Jan 1 1970 loop1
brw------- 1 root root 7, 2 Jan 1 1970 loop2
brw------- 1 root root 7, 3 Jan 1 1970 loop3
brw------- 1 root root 7, 4 Jan 1 1970 loop4
brw------- 1 root root 7, 5 Jan 1 1970 loop5
brw------- 1 root root 7, 6 Jan 1 1970 loop6
brw------- 1 root root 7, 7 Jan 1 1970 loop7
drwxr-xr-x 2 root root 60 Jan 1 1970 mapper
crw------- 1 root root 1, 1 Jan 1 1970 mem
crw------- 1 root root 245, 0 Nov 30 14:07 mhi_0001:01:00.0_LOOPBACK
crw------- 1 root root 511, 0 Nov 30 14:07 mhi_BHI
crw------- 1 root root 234, 1 Nov 30 14:07 mhi_DIAG
crw------- 1 root root 234, 3 Nov 30 14:07 mhi_DUN
crw------- 1 root root 234, 0 Nov 30 14:07 mhi_LOOPBACK
crw------- 1 root root 234, 2 Nov 30 14:07 mhi_QMI0
crw------- 1 root root 256, 0 Jan 1 1970 msm-rng
crw------- 1 root root 252, 0 Jan 1 1970 msm_sps
crw------- 1 root root 90, 0 Jan 1 1970 mtd0
crw------- 1 root root 90, 1 Jan 1 1970 mtd0ro
crw------- 1 root root 90, 2 Jan 1 1970 mtd1
crw------- 1 root root 90, 20 Jan 1 1970 mtd10
crw------- 1 root root 90, 21 Jan 1 1970 mtd10ro
crw------- 1 root root 90, 22 Jan 1 1970 mtd11
crw------- 1 root root 90, 23 Jan 1 1970 mtd11ro
crw------- 1 root root 90, 24 Jan 1 1970 mtd12
crw------- 1 root root 90, 25 Jan 1 1970 mtd12ro
crw------- 1 root root 90, 26 Jan 1 1970 mtd13
crw------- 1 root root 90, 27 Jan 1 1970 mtd13ro
crw------- 1 root root 90, 28 Jan 1 1970 mtd14
crw------- 1 root root 90, 29 Jan 1 1970 mtd14ro
crw------- 1 root root 90, 30 Jan 1 1970 mtd15
crw------- 1 root root 90, 31 Jan 1 1970 mtd15ro
crw------- 1 root root 90, 32 Jan 1 1970 mtd16
crw------- 1 root root 90, 33 Jan 1 1970 mtd16ro
crw------- 1 root root 90, 34 Jan 1 1970 mtd17
crw------- 1 root root 90, 35 Jan 1 1970 mtd17ro
crw------- 1 root root 90, 3 Jan 1 1970 mtd1ro
crw------- 1 root root 90, 4 Jan 1 1970 mtd2
crw------- 1 root root 90, 5 Jan 1 1970 mtd2ro
crw------- 1 root root 90, 6 Jan 1 1970 mtd3
crw------- 1 root root 90, 7 Jan 1 1970 mtd3ro
crw------- 1 root root 90, 8 Jan 1 1970 mtd4
crw------- 1 root root 90, 9 Jan 1 1970 mtd4ro
crw------- 1 root root 90, 10 Jan 1 1970 mtd5
crw------- 1 root root 90, 11 Jan 1 1970 mtd5ro
crw------- 1 root root 90, 12 Jan 1 1970 mtd6
crw------- 1 root root 90, 13 Jan 1 1970 mtd6ro
crw------- 1 root root 90, 14 Jan 1 1970 mtd7
crw------- 1 root root 90, 15 Jan 1 1970 mtd7ro
crw------- 1 root root 90, 16 Jan 1 1970 mtd8
crw------- 1 root root 90, 17 Jan 1 1970 mtd8ro
crw------- 1 root root 90, 18 Jan 1 1970 mtd9
crw------- 1 root root 90, 19 Jan 1 1970 mtd9ro
brw------- 1 root root 31, 0 Jan 1 1970 mtdblock0
brw------- 1 root root 31, 1 Jan 1 1970 mtdblock1
brw------- 1 root root 31, 10 Jan 1 1970 mtdblock10
brw------- 1 root root 31, 11 Jan 1 1970 mtdblock11
brw------- 1 root root 31, 12 Jan 1 1970 mtdblock12
brw------- 1 root root 31, 13 Jan 1 1970 mtdblock13
brw------- 1 root root 31, 14 Jan 1 1970 mtdblock14
brw------- 1 root root 31, 15 Jan 1 1970 mtdblock15
brw------- 1 root root 31, 16 Jan 1 1970 mtdblock16
brw------- 1 root root 31, 17 Jan 1 1970 mtdblock17
brw------- 1 root root 31, 2 Jan 1 1970 mtdblock2
brw------- 1 root root 31, 3 Jan 1 1970 mtdblock3
brw------- 1 root root 31, 4 Jan 1 1970 mtdblock4
brw------- 1 root root 31, 5 Jan 1 1970 mtdblock5
brw------- 1 root root 31, 6 Jan 1 1970 mtdblock6
brw------- 1 root root 31, 7 Jan 1 1970 mtdblock7
brw------- 1 root root 31, 8 Jan 1 1970 mtdblock8
brw------- 1 root root 31, 9 Jan 1 1970 mtdblock9
drwxr-xr-x 2 root root 60 Nov 30 14:07 net
crw-rw-rw- 1 root root 1, 3 Jan 1 1970 null
crw------- 1 root root 1, 4 Jan 1 1970 port
crw------- 1 root root 108, 0 Nov 30 14:07 ppp
crw-rw-rw- 1 root root 5, 2 Dec 2 23:14 ptmx
drwxr-xr-x 2 root root 0 Jan 1 1970 pts
brw------- 1 root root 1, 0 Jan 1 1970 ram0
brw------- 1 root root 1, 1 Jan 1 1970 ram1
brw------- 1 root root 1, 10 Jan 1 1970 ram10
brw------- 1 root root 1, 11 Jan 1 1970 ram11
brw------- 1 root root 1, 12 Jan 1 1970 ram12
brw------- 1 root root 1, 13 Jan 1 1970 ram13
brw------- 1 root root 1, 14 Jan 1 1970 ram14
brw------- 1 root root 1, 15 Jan 1 1970 ram15
brw------- 1 root root 1, 2 Jan 1 1970 ram2
brw------- 1 root root 1, 3 Jan 1 1970 ram3
brw------- 1 root root 1, 4 Jan 1 1970 ram4
brw------- 1 root root 1, 5 Jan 1 1970 ram5
brw------- 1 root root 1, 6 Jan 1 1970 ram6
brw------- 1 root root 1, 7 Jan 1 1970 ram7
brw------- 1 root root 1, 8 Jan 1 1970 ram8
brw------- 1 root root 1, 9 Jan 1 1970 ram9
crw-rw-rw- 1 root root 1, 8 Jan 1 1970 random
lrwxrwxrwx 1 root root 8 Jan 1 1970 shm -> /tmp/shm
drwxr-xr-x 2 root root 60 Jan 1 1970 snd
lrwxrwxrwx 1 root root 15 Jan 1 1970 stderr -> /proc/self/fd/2
lrwxrwxrwx 1 root root 15 Jan 1 1970 stdin -> /proc/self/fd/0
lrwxrwxrwx 1 root root 15 Jan 1 1970 stdout -> /proc/self/fd/1
crw------- 1 root root 10, 254 Nov 30 14:06 switch_ssdk
crw-rw-rw- 1 root root 5, 0 Jan 1 1970 tty
crw-rw---- 1 root dialout 235, 0 Nov 30 14:07 ttyBT0
crw-rw---- 1 root dialout 244, 0 Jan 1 1970 ttyEUD0
crw-rw---- 1 root dialout 243, 0 Dec 2 23:14 ttyMSM0
crw-rw---- 1 root dialout 188, 0 Nov 30 14:07 ttyUSB0
crw-rw---- 1 root dialout 188, 1 Nov 30 14:07 ttyUSB1
crw-rw---- 1 root dialout 188, 2 Nov 30 14:07 ttyUSB2
crw------- 1 root root 238, 0 Jan 1 1970 ubi0
crw------- 1 root root 238, 1 Jan 1 1970 ubi0_0
crw------- 1 root root 238, 2 Jan 1 1970 ubi0_1
crw------- 1 root root 238, 3 Jan 1 1970 ubi0_2
crw------- 1 root root 10, 60 Jan 1 1970 ubi_ctrl
brw------- 1 root root 253, 0 Jan 1 1970 ubiblock0_1
crw-rw-rw- 1 root root 1, 9 Jan 1 1970 urandom
crw------- 1 root root 10, 130 Jan 1 1970 watchdog
crw------- 1 root root 246, 0 Jan 1 1970 watchdog0
crw-rw-rw- 1 root root 1, 5 Jan 1 1970 zero@IceG: jak zrobisz cat /sys/kernel/debug/usb/devices na oryginalnym sofcie to widzisz modem? lspci ci go pokazuje?
z softu tego udostępnionego przez sprzedawce z allika
root@Exigo_Hub:~# cat /sys/kernel/debug/usb/devices
T: Bus=01 Lev=00 Prnt=00 Port=00 Cnt=00 Dev#= 1 Spd=480 MxCh= 1
B: Alloc= 0/800 us ( 0%), #Int= 0, #Iso= 0
D: Ver= 2.00 Cls=09(hub ) Sub=00 Prot=01 MxPS=64 #Cfgs= 1
P: Vendor=1d6b ProdID=0002 Rev= 5.04
S: Manufacturer=Linux 5.4.213 xhci-hcd
S: Product=xHCI Host Controller
S: SerialNumber=xhci-hcd.0.auto
C:* #Ifs= 1 Cfg#= 1 Atr=e0 MxPwr= 0mA
I:* If#= 0 Alt= 0 #EPs= 1 Cls=09(hub ) Sub=00 Prot=00 Driver=hub
E: Ad=81(I) Atr=03(Int.) MxPS= 4 Ivl=256ms
T: Bus=01 Lev=01 Prnt=01 Port=00 Cnt=01 Dev#= 2 Spd=480 MxCh= 0
D: Ver= 2.10 Cls=00(>ifc ) Sub=00 Prot=00 MxPS=64 #Cfgs= 1
P: Vendor=2c7c ProdID=0800 Rev= 4.14
S: Manufacturer=Quectel
S: Product=RM500Q-AE
S: SerialNumber=1a0d52e8
C:* #Ifs= 4 Cfg#= 1 Atr=a0 MxPwr=500mA
I:* If#= 0 Alt= 0 #EPs= 2 Cls=ff(vend.) Sub=ff Prot=30 Driver=option
E: Ad=81(I) Atr=02(Bulk) MxPS= 512 Ivl=0ms
E: Ad=01(O) Atr=02(Bulk) MxPS= 512 Ivl=0ms
I:* If#= 1 Alt= 0 #EPs= 3 Cls=ff(vend.) Sub=00 Prot=40 Driver=(none)
E: Ad=83(I) Atr=03(Int.) MxPS= 10 Ivl=32ms
E: Ad=82(I) Atr=02(Bulk) MxPS= 512 Ivl=0ms
E: Ad=02(O) Atr=02(Bulk) MxPS= 512 Ivl=0ms
I:* If#= 2 Alt= 0 #EPs= 3 Cls=ff(vend.) Sub=00 Prot=00 Driver=option
E: Ad=85(I) Atr=03(Int.) MxPS= 10 Ivl=32ms
E: Ad=84(I) Atr=02(Bulk) MxPS= 512 Ivl=0ms
E: Ad=03(O) Atr=02(Bulk) MxPS= 512 Ivl=0ms
I:* If#= 3 Alt= 0 #EPs= 3 Cls=ff(vend.) Sub=00 Prot=00 Driver=option
E: Ad=87(I) Atr=03(Int.) MxPS= 10 Ivl=32ms
E: Ad=86(I) Atr=02(Bulk) MxPS= 512 Ivl=0ms
E: Ad=04(O) Atr=02(Bulk) MxPS= 512 Ivl=0ms
T: Bus=02 Lev=00 Prnt=00 Port=00 Cnt=00 Dev#= 1 Spd=5000 MxCh= 1
B: Alloc= 0/800 us ( 0%), #Int= 0, #Iso= 0
D: Ver= 3.00 Cls=09(hub ) Sub=00 Prot=03 MxPS= 9 #Cfgs= 1
P: Vendor=1d6b ProdID=0003 Rev= 5.04
S: Manufacturer=Linux 5.4.213 xhci-hcd
S: Product=xHCI Host Controller
S: SerialNumber=xhci-hcd.0.auto
C:* #Ifs= 1 Cfg#= 1 Atr=e0 MxPwr= 0mA
I:* If#= 0 Alt= 0 #EPs= 1 Cls=09(hub ) Sub=00 Prot=00 Driver=hub
E: Ad=81(I) Atr=03(Int.) MxPS= 4 Ivl=256msroot@Exigo_Hub:~# lspci
0000:00:00.0 PCI bridge: Qualcomm Device 1004
0000:01:00.0 Unassigned class [ff00]: Qualcomm Device 0306
0001:00:00.0 PCI bridge: Qualcomm Device 1004
0001:01:00.0 Network controller: Qualcomm QCN6024/9024/9074 Wireless Network Adapter (rev 01)
root@Exigo_Hub:~# łapcie jeszcze wyciągnięty dts z routera przez ssh i pakiet DTC nwm może na coś przyda dla mnie to za dużo magi w tym ;p
/dts-v1/;
/ {
soc_version_major = <0x1000000>;
soc_version_minor = <0x1000000>;
#address-cells = <0x02>;
boot_version = [43 52 4d 2d 42 4f 4f 54 2e 42 46 2e 33 2e 33 2e 31 2e 31 2d 30 30 30 36 36 0a];
model = "D50 5G";
flash_type = <0xb000000>;
machid = <0x1000408>;
#size-cells = <0x02>;
tz_version = [43 52 4d 2d 54 5a 2e 57 4e 53 2e 34 2e 30 2d 30 30 30 38 39 0a];
interrupt-parent = <0x01>;
compatible = "qcom,ipq5018-ap-mp03.1\0qcom,ipq5018-mp03.1\0qcom,ipq5018\0brax,fa532";
cpu_type = <0xbf010000>;
hwlock {
syscon = <0x08 0x00 0x1000>;
compatible = "qcom,tcsr-mutex";
phandle = <0x0a>;
#hwlock-cells = <0x01>;
};
smem {
memory-region = <0x09>;
compatible = "qcom,smem";
hwlocks = <0x0a 0x03>;
};
qti,sps {
compatible = "qti,msm-sps-4k";
qti,pipe-attr-ee;
};
ctx-save {
memory-region = <0x58>;
compatible = "qti,ctxt-save-ipq5018";
};
srd_trace {
compatible = "srd";
};
thermal-zones {
status = "ok";
tsens_tz_sensor3 {
polling-delay = <0x00>;
polling-delay-passive = <0x00>;
thermal-sensors = <0x59 0x03>;
trips {
cpu-config-hi {
temperature = <0x186a0>;
hysteresis = <0x02>;
type = "configurable_hi";
};
cpu-critical-hi {
temperature = <0x1d4c0>;
hysteresis = <0x02>;
type = "critical_high";
};
cpu-config-lo {
temperature = <0x15f90>;
hysteresis = <0x02>;
type = "configurable_lo";
};
cpu-critical-low {
temperature = <0x00>;
hysteresis = <0x02>;
type = "critical_low";
};
};
};
tsens_tz_sensor1 {
polling-delay = <0x00>;
polling-delay-passive = <0x00>;
thermal-sensors = <0x59 0x01>;
trips {
cpu-config-hi {
temperature = <0x186a0>;
hysteresis = <0x02>;
type = "configurable_hi";
};
cpu-critical-hi {
temperature = <0x1d4c0>;
hysteresis = <0x02>;
type = "critical_high";
};
cpu-config-lo {
temperature = <0x15f90>;
hysteresis = <0x02>;
type = "configurable_lo";
};
cpu-critical-low {
temperature = <0x00>;
hysteresis = <0x02>;
type = "critical_low";
};
};
};
tsens_tz_sensor4 {
polling-delay = <0x00>;
polling-delay-passive = <0x00>;
thermal-sensors = <0x59 0x04>;
trips {
cpu-config-hi {
temperature = <0x186a0>;
hysteresis = <0x02>;
type = "configurable_hi";
};
cpu-critical-hi {
temperature = <0x1d4c0>;
hysteresis = <0x02>;
type = "critical_high";
};
cpu-config-lo {
temperature = <0x15f90>;
hysteresis = <0x02>;
type = "configurable_lo";
};
cpu-critical-low {
temperature = <0x00>;
hysteresis = <0x02>;
type = "critical_low";
};
};
};
tsens_tz_sensor2 {
polling-delay = <0x00>;
polling-delay-passive = <0x00>;
thermal-sensors = <0x59 0x02>;
trips {
cpu-config-hi {
temperature = <0x186a0>;
hysteresis = <0x02>;
type = "configurable_hi";
};
cpu-critical-hi {
temperature = <0x1d4c0>;
hysteresis = <0x02>;
type = "critical_high";
};
cpu-config-lo {
temperature = <0x15f90>;
hysteresis = <0x02>;
type = "configurable_lo";
};
cpu-critical-low {
temperature = <0x00>;
hysteresis = <0x02>;
type = "critical_low";
};
};
};
};
soc {
dma-ranges;
#address-cells = <0x01>;
#size-cells = <0x01>;
compatible = "simple-bus";
ranges = <0x00 0x00 0x00 0xffffffff>;
qpic-nand@79b0000 {
pinctrl-names = "default";
#address-cells = <0x01>;
pinctrl-0 = <0x1e>;
clock-names = "core\0aon\0io_macro";
clocks = <0x0b 0x68 0x0b 0x67 0x0b 0x69>;
#size-cells = <0x00>;
dma-names = "tx\0rx\0cmd\0sts";
qcom,phase = <0x05>;
qcom,io_macro_clk_rates = <0x16e3600 0x5f5e100 0xbebc200 0x1312d000>;
compatible = "qcom,ebi2-nandc-bam-v2.1.1";
qcom,io_macro_max_clk = <0x1312d000>;
status = "ok";
reg = <0x79b0000 0x10000>;
dmas = <0x1d 0x00 0x1d 0x01 0x1d 0x02 0x1d 0x03>;
qcom,training_offset = <0x980000>;
qcom,iomacromax_clk = <0x1312d000>;
nandcs@0 {
#address-cells = <0x01>;
nand-ecc-step-size = <0x200>;
#size-cells = <0x01>;
compatible = "qcom,nandcs";
reg = <0x00>;
nand-ecc-strength = <0x04>;
nand-bus-width = <0x08>;
partition@380000 {
label = "0:DEVCFG";
reg = <0x380000 0x40000>;
};
partition@980000 {
label = "0:TRAINING";
reg = <0x980000 0x80000>;
};
partition@280000 {
label = "0:QSEE_1";
reg = <0x280000 0x100000>;
};
partition@3c0000 {
label = "0:DEVCFG_1";
reg = <0x3c0000 0x40000>;
};
partition@880000 {
label = "0:XUCERT";
reg = <0x880000 0x100000>;
};
partition@100000 {
label = "0:BOOTCONFIG";
reg = <0x100000 0x40000>;
};
partition@a00000 {
label = "rootfs";
reg = <0xa00000 0x3a00000>;
};
partition@140000 {
label = "0:BOOTCONFIG1";
reg = <0x140000 0x40000>;
};
partition@180000 {
label = "0:QSEE";
reg = <0x180000 0x100000>;
};
partition@780000 {
label = "0:ART";
reg = <0x780000 0x100000>;
};
partition@0 {
label = "0:SBL1";
reg = <0x00 0x80000>;
};
partition@80000 {
label = "0:MIBIB";
reg = <0x80000 0x80000>;
};
partition@640000 {
label = "0:APPSBL_1";
reg = <0x640000 0x140000>;
};
partition@500000 {
label = "0:APPSBL";
reg = <0x500000 0x140000>;
};
partition@400000 {
label = "0:CDT";
reg = <0x400000 0x40000>;
};
partition@440000 {
label = "0:CDT_1";
reg = <0x440000 0x40000>;
};
partition@480000 {
label = "0:APPSBLENV";
reg = <0x480000 0x80000>;
};
partition@4400000 {
label = "rootfs_1";
reg = <0x4400000 0x3a00000>;
};
};
};
cti@601e000 {
arm,primecell-periphid = <0x3b966>;
clock-names = "apb_pclk\0core_a_clk";
reg-names = "cti-base";
clocks = <0x0b 0x61 0x0b 0x5e>;
coresight-name = "coresight-cti14";
compatible = "arm,primecell";
reg = <0x601e000 0x1000>;
};
tmc@6047000 {
arm,primecell-periphid = <0xbb961>;
coresight-ctis = <0x33 0x34>;
clock-names = "apb_pclk\0core_a_clk";
reg-names = "tmc-base";
clocks = <0x0b 0x61 0x0b 0x5e>;
coresight-name = "coresight-tmc-etf";
arm,default-sink;
compatible = "arm,primecell";
reg = <0x6047000 0x1000>;
ports {
#address-cells = <0x01>;
#size-cells = <0x00>;
port@0 {
reg = <0x00>;
endpoint {
remote-endpoint = <0x39>;
phandle = <0x38>;
};
};
port@1 {
reg = <0x00>;
endpoint {
slave-mode;
remote-endpoint = <0x3a>;
phandle = <0x3b>;
};
};
};
};
cti@601b000 {
arm,primecell-periphid = <0x3b966>;
clock-names = "apb_pclk\0core_a_clk";
reg-names = "cti-base";
clocks = <0x0b 0x61 0x0b 0x5e>;
coresight-name = "coresight-cti11";
compatible = "arm,primecell";
reg = <0x601b000 0x1000>;
};
wifi2@c000000 {
interrupts = <0x00 0x1c0 0x01>;
compatible = "qcom,cnss-qcn6122\0qcom,qcn6122-wifi";
status = "disabled";
msi-parent = <0x23>;
};
cti@6198000 {
arm,primecell-periphid = <0x3b966>;
clock-names = "apb_pclk\0core_a_clk";
reg-names = "cti-base";
clocks = <0x0b 0x61 0x0b 0x5e>;
cpu = <0x4a>;
coresight-name = "coresight-cti-cpu0";
compatible = "arm,primecell";
reg = <0x6198000 0x1000>;
};
crypto@73a000 {
clock-names = "iface\0bus\0core";
clocks = <0x0b 0x2c 0x0b 0x2d 0x0b 0x2e>;
qce,cmd_desc_support;
dma-names = "rx\0tx";
compatible = "qcom,crypto-v5.1";
reg = <0x73a000 0x6000>;
dmas = <0x13 0x02 0x13 0x03>;
};
funnel@61a1000 {
arm,primecell-periphid = <0xbb908>;
clock-names = "apb_pclk\0core_a_clk";
reg-names = "funnel-base";
clocks = <0x0b 0x61 0x0b 0x5e>;
coresight-name = "coresight-funnel-apss0";
compatible = "arm,primecell";
reg = <0x61a1000 0x1000>;
ports {
#address-cells = <0x01>;
#size-cells = <0x00>;
port@0 {
reg = <0x00>;
endpoint {
remote-endpoint = <0x47>;
phandle = <0x45>;
};
};
port@1 {
reg = <0x00>;
endpoint {
slave-mode;
remote-endpoint = <0x48>;
phandle = <0x4b>;
};
};
port@2 {
reg = <0x01>;
endpoint {
slave-mode;
remote-endpoint = <0x49>;
phandle = <0x4d>;
};
};
};
};
syscon@193d100 {
compatible = "syscon";
reg = <0x193d100 0x04>;
phandle = <0x19>;
};
lpass@0xA000000 {
clock-names = "snoc_axim\0snoc_sway\0axim\0sway";
resets = <0x0b 0x1d>;
clocks = <0x0b 0x72 0x0b 0x73 0x0b 0x45 0x0b 0x46>;
compatible = "qca,lpass-ipq5018";
status = "disabled";
reg = <0xa000000 0x3bffff>;
reset-names = "lpass";
};
dma@704000 {
clock-names = "bam_clk";
qti,config-pipe-trust-reg = <0x00>;
interrupts = <0x00 0xcf 0x04>;
clocks = <0x0b 0x2c>;
qcom,controlled-remotely = <0x01>;
compatible = "qcom,bam-v1.7.0";
reg = <0x704000 0x20000>;
phandle = <0x13>;
qcom,ee = <0x01>;
#dma-cells = <0x01>;
};
cti@6018000 {
arm,primecell-periphid = <0x3b966>;
clock-names = "apb_pclk\0core_a_clk";
reg-names = "cti-base";
clocks = <0x0b 0x61 0x0b 0x5e>;
coresight-name = "coresight-cti8";
compatible = "arm,primecell";
reg = <0x6018000 0x1000>;
phandle = <0x34>;
};
cti@6015000 {
arm,primecell-periphid = <0x3b966>;
clock-names = "apb_pclk\0core_a_clk";
reg-names = "cti-base";
clocks = <0x0b 0x61 0x0b 0x5e>;
coresight-name = "coresight-cti5";
compatible = "arm,primecell";
reg = <0x6015000 0x1000>;
};
dp2 {
phy-mode = "sgmii";
clock-names = "nss-snoc-gmac-axi-clk";
qcom,id = <0x02>;
local-mac-address = [00 00 00 00 00];
interrupts = <0x00 0x6d 0x04>;
clocks = <0x0b 0x71>;
device_type = "network";
qcom,rx-page-mode = <0x00>;
compatible = "qcom,nss-dp";
qcom,mactype = <0x02>;
reg = <0x39d00000 0x10000>;
phandle = <0x0e>;
};
cti@6012000 {
arm,primecell-periphid = <0x3b966>;
clock-names = "apb_pclk\0core_a_clk";
reg-names = "cti-base";
clocks = <0x0b 0x61 0x0b 0x5e>;
coresight-name = "coresight-cti2";
compatible = "arm,primecell";
reg = <0x6012000 0x1000>;
};
hs_m31phy@5b000 {
reg-names = "m31usb_phy_base\0qscratch_base";
phy_type = "utmi";
resets = <0x0b 0x4f>;
compatible = "qca,m31-usb-hsphy";
status = "ok";
reg = <0x5b000 0x120 0x8af8800 0x400>;
phandle = <0x20>;
reset-names = "usb2_phy_reset";
};
spi@78b5000 {
pinctrl-names = "default";
#address-cells = <0x01>;
pinctrl-0 = <0x1b>;
clock-names = "core\0iface";
cs-select = <0x00>;
interrupts = <0x00 0x5f 0x04>;
clocks = <0x0b 0x1b 0x0b 0x19>;
#size-cells = <0x00>;
spi-max-frequency = <0x2faf080>;
dma-names = "tx\0rx";
compatible = "qcom,spi-qup-v2.2.1";
status = "ok";
reg = <0x78b5000 0x600>;
dmas = <0x1a 0x04 0x1a 0x05>;
m25p80@0 {
#address-cells = <0x01>;
linux,modalias = "m25p80\0n25q128a11";
#size-cells = <0x01>;
spi-max-frequency = <0x2faf080>;
compatible = "n25q128a11";
use-default-sizes;
reg = <0x00>;
};
};
funnel@6120000 {
arm,primecell-periphid = <0xbb908>;
clock-names = "apb_pclk\0core_a_clk";
reg-names = "funnel-base";
clocks = <0x0b 0x61 0x0b 0x5e>;
coresight-name = "coresight-funnel-right";
compatible = "arm,primecell";
reg = <0x6120000 0x1000>;
ports {
#address-cells = <0x01>;
#size-cells = <0x00>;
port@0 {
reg = <0x00>;
endpoint {
remote-endpoint = <0x44>;
phandle = <0x3d>;
};
};
port@1 {
reg = <0x03>;
endpoint {
slave-mode;
remote-endpoint = <0x45>;
phandle = <0x47>;
};
};
};
};
scm {
compatible = "qcom,scm";
qcom,dload-mode = <0x19 0x00>;
};
clock-controller@b198000 {
compatible = "qcom,arm-cortex-acc";
reg = <0xb198000 0x1000>;
phandle = <0x05>;
};
serial@78b0000 {
pinctrl-names = "default";
pinctrl-0 = <0x1f>;
clock-names = "core\0iface";
interrupts = <0x00 0x6c 0x04>;
clocks = <0x0b 0x22 0x0b 0x19>;
compatible = "qcom,msm-uartdm-v1.4\0qcom,msm-uartdm";
status = "disabled";
reg = <0x78b0000 0x200>;
};
usb3@8A00000 {
#address-cells = <0x01>;
clock-names = "sys_noc_axi\0master\0sleep\0mock_utmi\0cfg_ahb_clk\0aux_clk\0lfps_clk\0pipe_clk";
reg-names = "qscratch_base\0dwc3_base";
assigned-clocks = <0x0b 0x7b 0x0b 0x8d 0x0b 0x8e>;
assigned-clock-rates = <0x7f27450 0x7f27450 0x3938700>;
resets = <0x0b 0x62>;
clocks = <0x0b 0x7b 0x0b 0x8d 0x0b 0x90 0x0b 0x8e 0x0b 0x8f 0x0b 0x8a 0x0b 0x8c 0x0b 0xc5>;
#size-cells = <0x01>;
device-power-gpio = <0x0d 0x18 0x01>;
compatible = "qcom,ipq5018-dwc3";
ranges;
status = "ok";
reg = <0x8af8800 0x100 0x8a00000 0xe000>;
reset-names = "usb30_mstr_rst";
qcom,select-utmi-as-pipe-clk;
qca,host = <0x01>;
dwc3@8A00000 {
snps,hird-threshold = [00];
tx-fifo-resize;
snps,nominal-elastic-buffer;
snps,is-utmi-l1-suspend;
phy-names = "usb3-phy";
snps,quirk-ref-clock-adjustment = <0x49459>;
snps,usb3-u1u2-disable;
snps,dis_u2_susphy_quirk;
snps,dis_ep_cache_eviction;
interrupts = <0x00 0x8c 0x04>;
#phy-cells = <0x00>;
compatible = "snps,dwc3";
snps,dis_u3_susphy_quirk;
snps,quirk-30m-sb-sel = <0x00>;
phys = <0x21>;
reg = <0x8a00000 0xe000>;
usb-phy = <0x20>;
dr_mode = "host";
snps,quirk-ref-clock-period = <0x10>;
};
};
i2c@78b7000 {
pinctrl-names = "default";
#address-cells = <0x01>;
pinctrl-0 = <0x1c>;
clock-names = "iface\0core";
interrupts = <0x00 0x61 0x04>;
clocks = <0x0b 0x19 0x0b 0x1e>;
#size-cells = <0x00>;
clock-frequency = <0x61a80>;
dma-names = "rx\0tx";
compatible = "qcom,i2c-qup-v2.2.1";
status = "disabled";
reg = <0x78b7000 0x600>;
dmas = <0x1a 0x09 0x1a 0x08>;
};
tpda@6004000 {
arm,primecell-periphid = <0x3b969>;
qcom,cmb-elem-size = <0x00 0x20>;
clock-names = "apb_pclk\0core_a_clk";
reg-names = "tpda-base";
clocks = <0x0b 0x61 0x0b 0x5e>;
coresight-name = "coresight-tpda";
compatible = "arm,primecell";
qcom,tpda-atid = <0x40>;
reg = <0x6004000 0x1000>;
ports {
#address-cells = <0x01>;
#size-cells = <0x00>;
port@0 {
reg = <0x00>;
endpoint {
remote-endpoint = <0x51>;
phandle = <0x3f>;
};
};
port@1 {
reg = <0x00>;
endpoint {
slave-mode;
remote-endpoint = <0x52>;
phandle = <0x53>;
};
};
};
};
cti@610c000 {
arm,primecell-periphid = <0x3b966>;
clock-names = "apb_pclk\0core_a_clk";
reg-names = "cti-base";
clocks = <0x0b 0x61 0x0b 0x5e>;
coresight-name = "coresight-cti-rpm-cpu0";
compatible = "arm,primecell";
reg = <0x610c000 0x1000>;
};
interrupt-controller@b000000 {
interrupts = <0x01 0x09 0x04>;
compatible = "qcom,msm-qgic2";
ranges = <0x00 0xb00a000 0x1ffa>;
#interrupt-cells = <0x03>;
reg = <0xb000000 0x1000 0xb002000 0x1000 0xb001000 0x1000 0xb004000 0x1000>;
phandle = <0x01>;
interrupt-controller;
v2m@1000 {
msi-controller;
compatible = "arm,gic-v2m-frame";
reg = <0x1000 0xffd>;
};
v2m@0 {
msi-controller;
compatible = "arm,gic-v2m-frame";
reg = <0x00 0xffd>;
phandle = <0x23>;
};
};
qcom,msm-imem@8600000 {
#address-cells = <0x01>;
#size-cells = <0x01>;
compatible = "qcom,msm-imem";
ranges = <0x00 0x8600000 0x1000>;
reg = <0x8600000 0x1000>;
restart-reason-buf-addr@7a4 {
compatible = "qcom,msm-imem-restart-reason-buf-addr";
reg = <0x7a4 0x04>;
};
};
etm@619d000 {
arm,primecell-periphid = <0xbb95d>;
clock-names = "apb_pclk\0core_a_clk";
clocks = <0x0b 0x61 0x0b 0x5e>;
cpu = <0x4c>;
coresight-name = "coresight-etm1";
compatible = "arm,primecell";
reg = <0x619d000 0x1000>;
port {
endpoint {
remote-endpoint = <0x4d>;
phandle = <0x49>;
};
};
};
ess-instance {
num_devices = <0x02>;
ess-switch@0x39c00000 {
switch_mac_mode = <0x0f>;
device_id = <0x00>;
clock-names = "cmn_ahb_clk\0cmn_sys_clk\0uniphy_ahb_clk\0uniphy_sys_clk\0gcc_mdio0_ahb_clk\0gcc_mdio1_ahb_clk\0gcc_gmac0_cfg_clk\0gcc_gmac0_sys_clk\0gcc_gmac1_cfg_clk\0gcc_gmac1_sys_clk\0uniphy0_port1_rx_clk\0uniphy0_port1_tx_clk\0uniphy1_port5_rx_clk\0uniphy1_port5_tx_clk\0nss_port1_rx_clk\0nss_port1_tx_clk\0nss_port2_rx_clk\0nss_port2_tx_clk\0gcc_snoc_gmac0_ahb_clk\0gcc_snoc_gmac1_ahb_clk\0gcc_gmac0_ptp_clk\0gcc_gmac1_ptp_clk";
resets = <0x0b 0x11 0x0b 0x5d 0x0b 0x16 0x0b 0x19 0x0b 0x6e 0x0b 0x6f>;
clocks = <0x0b 0x28 0x0b 0x29 0x0b 0x86 0x0b 0x88 0x0b 0x47 0x0b 0x48 0x0b 0x37 0x0b 0x3a 0x0b 0x3c 0x0b 0x3f 0x0b 0x35 0x0b 0x36 0x0b 0x87 0x0b 0x89 0x0b 0x39 0x0b 0x3b 0x0b 0x3e 0x0b 0x40 0x0b 0x6e 0x0b 0x70 0x0b 0x38 0x0b 0x3d>;
switch_access_mode = "local bus";
compatible = "qcom,ess-switch-ipq50xx";
cmnblk_clk = "internal_96MHz";
reg = <0x39c00000 0x200000>;
reset-names = "gephy_bcr_rst\0uniphy_bcr_rst\0gmac0_bcr_rst\0gmac1_bcr_rst\0uniphy1_soft_rst\0gephy_misc_rst";
qcom,port_phyinfo {
port@0 {
port_id = <0x01>;
phy_address = <0x07>;
};
port@1 {
port_id = <0x02>;
forced-speed = <0x3e8>;
forced-duplex = <0x01>;
};
};
led_source@0 {
source = <0x00>;
mode = "normal";
speed = "all";
active = "high";
blink_en = "enable";
};
};
ess-switch1@1 {
device_id = <0x01>;
mdio-bus = <0x14>;
switch_access_mode = "mdio";
reset_gpio = <0x0d 0x27 0x00>;
switch_lan_bmp = <0x1e>;
compatible = "qcom,ess-switch-qca83xx";
switch_wan_bmp = <0x00>;
qca,ar8327-initvals = <0x04 0x7600000 0x08 0x1000000 0x0c 0x80 0x10 0x2613a0 0xe4 0xaa545 0xe0 0xc74164de 0x7c 0x4e 0x94 0x4e>;
switch_cpu_bmp = <0x40>;
qcom,port_phyinfo {
port@0 {
port_id = <0x01>;
phy_address = <0x00>;
};
port@3 {
port_id = <0x04>;
phy_address = <0x03>;
};
port@1 {
port_id = <0x02>;
phy_address = <0x01>;
};
port@2 {
port_id = <0x03>;
phy_address = <0x02>;
};
};
};
};
phy@7e000 {
clock-names = "pipe_clk";
phy-type = "gen2";
resets = <0x0b 0x2f 0x0b 0x30>;
clocks = <0x0b 0xc3>;
#phy-cells = <0x00>;
compatible = "qca,uni-pcie-phy-gen2";
status = "ok";
reg = <0x7e000 0x800>;
phandle = <0x22>;
reset-names = "phy\0phy_phy";
mode-fixed = <0x02>;
};
cti@601d000 {
arm,primecell-periphid = <0x3b966>;
clock-names = "apb_pclk\0core_a_clk";
reg-names = "cti-base";
clocks = <0x0b 0x61 0x0b 0x5e>;
coresight-name = "coresight-cti13";
compatible = "arm,primecell";
reg = <0x601d000 0x1000>;
};
stm@6002000 {
arm,primecell-periphid = <0xbb962>;
clock-names = "apb_pclk\0core_a_clk";
reg-names = "stm-base\0stm-stimulus-base";
clocks = <0x0b 0x61 0x0b 0x5e>;
coresight-name = "coresight-stm";
compatible = "arm,primecell";
reg = <0x6002000 0x1000 0x9280000 0x180000>;
port {
endpoint {
remote-endpoint = <0x4f>;
phandle = <0x40>;
};
};
};
qcom,sps {
status = "ok";
};
cti@601a000 {
arm,primecell-periphid = <0x3b966>;
clock-names = "apb_pclk\0core_a_clk";
reg-names = "cti-base";
clocks = <0x0b 0x61 0x0b 0x5e>;
coresight-name = "coresight-cti10";
compatible = "arm,primecell";
reg = <0x601a000 0x1000>;
};
qcom,nss_crypto {
#address-cells = <0x01>;
qcom,max-contexts = <0x40>;
#size-cells = <0x01>;
compatible = "qcom,nss-crypto";
ranges;
qcom,max-context-size = <0x90>;
ce5_node {
qcom,sha160-hmac;
qcom,3des-cbc-sha160-hmac;
reg-names = "crypto_pbase\0bam_base";
qcom,transform-enabled;
qcom,aes128-cbc-sha256-hmac;
qcom,3des-cbc;
qcom,aes256-cbc-sha256-hmac;
qcom,aes128-ecb;
qcom,aes128-cbc-sha160-hmac;
qcom,aes128-cbc;
qcom,aes128-ctr-sha256-hmac;
qcom,aes256-cbc-sha160-hmac;
qcom,aes256-ctr-sha256-hmac;
compatible = "qcom,ce5";
qcom,aes128-ctr;
qcom,dma-mask = <0x0c>;
qcom,aes128-ctr-sha160-hmac;
qcom,aes256-ecb;
qcom,sha256-hash;
reg = <0x73a000 0x6000 0x704000 0x20000>;
qcom,aes256-ctr-sha160-hmac;
qcom,aes256-cbc;
qcom,sha256-hmac;
qcom,sha160-hash;
qcom,aes256-ctr;
qcom,3des-cbc-sha256-hmac;
engine0 {
qcom,ee = <0x02 0x03>;
};
};
};
leds {
pinctrl-names = "default";
pinctrl-0 = <0x57>;
compatible = "gpio-leds";
led_nr_r {
linux,default-trigger = "led_nr_r";
label = "led_nr_r";
default-state = "off";
gpios = <0x0d 0x22 0x00>;
};
led_lte_g {
linux,default-trigger = "led_lte_g";
label = "led_lte_g";
default-state = "off";
gpios = <0x0d 0x23 0x00>;
};
led_mesh_g {
linux,default-trigger = "led_mesh_g";
label = "led_mesh_g";
default-state = "on";
gpios = <0x0d 0x1b 0x00>;
};
led_wifi {
linux,default-trigger = "led_wifi";
label = "led_wifi";
default-state = "off";
gpios = <0x0d 0x1e 0x00>;
};
led_modem {
linux,default-trigger = "led_voice";
label = "led_modem";
default-state = "off";
gpios = <0x0d 0x01 0x00>;
};
led_mesh_r {
linux,default-trigger = "led_mesh_r";
label = "led_mesh_r";
default-state = "off";
gpios = <0x0d 0x1c 0x00>;
};
led_nr_g {
linux,default-trigger = "led_nr_g";
label = "led_nr_g";
default-state = "off";
gpios = <0x0d 0x21 0x00>;
};
};
syscon@1905000 {
compatible = "syscon";
reg = <0x1905000 0x20000>;
phandle = <0x08>;
};
phy@86000 {
clock-names = "pipe_clk";
phy-type = "gen2";
resets = <0x0b 0x23 0x0b 0x24>;
clocks = <0x0b 0xc2>;
#phy-cells = <0x00>;
x2 = <0x01>;
compatible = "qca,uni-pcie-phy-gen2";
status = "ok";
reg = <0x86000 0x1000>;
phandle = <0x26>;
reset-names = "phy\0phy_phy";
mode-fixed = <0x02>;
};
pinctrl@1000000 {
pinctrl-names = "default";
pinctrl-0 = <0x15 0x16>;
gpio-controller;
interrupts = <0x00 0xd0 0x04>;
compatible = "qcom,ipq5018-pinctrl";
#interrupt-cells = <0x02>;
reg = <0x1000000 0x300000>;
phandle = <0x0d>;
#gpio-cells = <0x02>;
gpio-ranges = <0x0d 0x00 0x00 0x2f>;
interrupt-controller;
audio_pinmux {
phandle = <0x32>;
mux_2 {
function = "audio_rxfsync";
pins = "gpio25";
drive-strength = <0x08>;
bias-pull-down;
};
mux_7 {
function = "audio_txd";
pins = "gpio30";
drive-strength = <0x08>;
bias-pull-down;
};
mux_5 {
function = "audio_txbclk";
pins = "gpio28";
drive-strength = <0x08>;
bias-pull-down;
};
mux_3 {
function = "audio_rxd";
pins = "gpio26";
drive-strength = <0x08>;
bias-pull-down;
};
mux_1 {
function = "audio_rxbclk";
pins = "gpio24";
drive-strength = <0x08>;
bias-pull-down;
};
mux_6 {
function = "audio_txfsync";
pins = "gpio29";
drive-strength = <0x08>;
bias-pull-down;
};
mux_4 {
function = "audio_txmclk";
pins = "gpio27";
drive-strength = <0x08>;
bias-pull-down;
};
};
blsp0_spi_pins {
phandle = <0x1b>;
mux {
function = "blsp0_spi";
pins = "gpio10\0gpio11\0gpio12\0gpio13";
drive-strength = <0x02>;
bias-disable;
};
};
blsp1_uart_pins {
phandle = <0x1f>;
blsp1_uart_rx_tx {
function = "blsp1_uart2";
pins = "gpio23\0gpio25\0gpio24\0gpio26";
bias-disable;
};
};
phy_led_pins {
phandle = <0x16>;
gephy_led_pin {
function = "led0";
pins = "gpio46";
drive-strength = <0x08>;
bias-pull-down;
};
};
mdio_pinmux {
phandle = <0x0c>;
mux_0 {
function = "mdc";
pins = "gpio36";
drive-strength = <0x08>;
bias-pull-up;
};
mux_1 {
function = "mdio";
pins = "gpio37";
drive-strength = <0x08>;
bias-pull-up;
};
};
ap2mdm_status {
function = "gpio";
pins = "gpio25";
drive-strength = <0x08>;
output-high;
bias-pull-up;
};
pcie1_wake_gpio {
function = "pcie1_wake";
pins = "gpio19";
drive-strength = <0x08>;
phandle = <0x24>;
bias-pull-up;
};
mdm2ap_e911_status {
pins = "gpio0";
drive-strength = <0x08>;
bias-pull-down;
phandle = <0x25>;
};
qspi_nand_pins {
phandle = <0x1e>;
qspi_cs {
function = "qspi_cs";
pins = "gpio8";
drive-strength = <0x08>;
bias-disable;
};
qspi_clock {
function = "qspi_clk";
pins = "gpio9";
drive-strength = <0x08>;
bias-disable;
};
qspi_data {
function = "qspi_data";
pins = "gpio4\0gpio5\0gpio6\0gpio7";
drive-strength = <0x08>;
bias-disable;
};
};
i2c_pins {
phandle = <0x1c>;
i2c_scl {
function = "blsp2_i2c1";
pins = "gpio25";
drive-strength = <0x08>;
bias-disable;
};
i2c_sda {
function = "blsp2_i2c1";
pins = "gpio26";
drive-strength = <0x08>;
bias-disable;
};
};
blsp0_uart_pins {
phandle = <0x15>;
blsp0_uart_rx_tx {
function = "blsp0_uart0";
pins = "gpio20\0gpio21";
bias-disable;
};
};
button_pins {
phandle = <0x56>;
mux {
function = "gpio";
pins = "gpio22\0gpio38";
drive-strength = <0x08>;
bias-pull-up;
};
};
led_mux {
phandle = <0x57>;
mux {
function = "gpio";
pins = "gpio1\0gpio27\0gpio28\0gpio30\0gpio33\0gpio34\0gpio35";
drive-strength = <0x08>;
output-low;
};
};
};
pci@a0000000 {
#address-cells = <0x03>;
phy-names = "pciephy";
bus-range = <0x00 0xff>;
clock-names = "iface\0axi_m\0axi_s\0ahb\0aux\0axi_bridge";
reg-names = "dbi\0elbi\0atu\0parf\0config\0system_noc";
axi-halt-val = <0x1e>;
resets = <0x0b 0x25 0x0b 0x26 0x0b 0x27 0x0b 0x28 0x0b 0x29 0x0b 0x2a 0x0b 0x2b 0x0b 0x2c>;
interrupts = <0x00 0x33 0x04>;
clocks = <0x0b 0x77 0x0b 0x4c 0x0b 0x4e 0x0b 0x4a 0x0b 0x4b 0x0b 0x4d>;
interrupt-map = <0x00 0x00 0x00 0x01 0x01 0x00 0x4b 0x04 0x00 0x00 0x00 0x02 0x01 0x00 0x4e 0x04 0x00 0x00 0x00 0x03 0x01 0x00 0x4f 0x04 0x00 0x00 0x00 0x04 0x01 0x00 0x53 0x04>;
#size-cells = <0x02>;
device_type = "pci";
interrupt-map-mask = <0x00 0x00 0x00 0x07>;
num-lanes = <0x02>;
compatible = "qcom,pcie-ipq5018";
ranges = <0x81000000 0x00 0xa0200000 0xa0200000 0x00 0x100000 0x82000000 0x00 0xa0300000 0xa0300000 0x00 0x10000000>;
#interrupt-cells = <0x01>;
status = "ok";
interrupt-names = "global_irq";
phys = <0x26>;
reg = <0xa0000000 0xf1d 0xa0000f20 0xa8 0xa0001000 0x1000 0x80000 0x3000 0xa0100000 0x1000 0x560608 0x04>;
linux,pci-domain = <0x01>;
msi-parent = <0x23>;
reset-names = "pipe\0sleep\0sticky\0axi_m\0axi_s\0ahb\0axi_m_sticky\0axi_s_sticky";
perst-gpio = <0x0d 0x0f 0x01>;
pcie_x2_rp {
status = "ok";
reg = <0x00 0x00 0x00 0x00 0x00>;
qcom,mhi@1 {
#address-cells = <0x02>;
memory-region = <0x00 0x27>;
#size-cells = <0x02>;
qti,rddm-seg-len = <0x1000>;
qti,disable-rddm-prealloc;
reg = <0x00 0x00 0x00 0x00 0x00>;
qrtr_instance_id = <0x20>;
};
};
};
syscon@1945000 {
compatible = "syscon";
reg = <0x1945000 0xe000>;
phandle = <0x29>;
};
mailbox@b111000 {
#mbox-cells = <0x01>;
#clock-cells = <0x01>;
compatible = "qcom,ipq5018-apcs-apps-global";
reg = <0xb111000 0x6000>;
phandle = <0x04>;
};
funnel@6130000 {
arm,primecell-periphid = <0xbb908>;
clock-names = "apb_pclk\0core_a_clk";
reg-names = "funnel-base";
clocks = <0x0b 0x61 0x0b 0x5e>;
coresight-name = "coresight-funnel-mm";
compatible = "arm,primecell";
reg = <0x6130000 0x1000>;
ports {
#address-cells = <0x01>;
#size-cells = <0x00>;
port@0 {
reg = <0x00>;
endpoint {
remote-endpoint = <0x46>;
phandle = <0x3e>;
};
};
port@1 {
reg = <0x06>;
endpoint {
slave-mode;
};
};
};
};
wifi1@c000000 {
interrupts = <0x00 0x1a0 0x01>;
compatible = "qcom,cnss-qcn6122\0qcom,qcn6122-wifi";
status = "disabled";
msi-parent = <0x23>;
};
cti@6017000 {
arm,primecell-periphid = <0x3b966>;
clock-names = "apb_pclk\0core_a_clk";
reg-names = "cti-base";
clocks = <0x0b 0x61 0x0b 0x5e>;
coresight-name = "coresight-cti7";
compatible = "arm,primecell";
reg = <0x6017000 0x1000>;
};
qrng@e3000 {
clock-names = "km_clk_src";
qcom,no-qrng-config;
clocks = <0x0b 0x54>;
compatible = "qcom,msm-rng";
reg = <0xe3000 0x1000>;
};
gpio_keys {
pinctrl-names = "default";
pinctrl-0 = <0x56>;
compatible = "gpio-keys";
button@0 {
label = "reset";
linux,input-type = <0x01>;
linux,code = <0x198>;
debounce-interval = <0x3c>;
gpios = <0x0d 0x16 0x01>;
};
button@1 {
label = "wps";
linux,input-type = <0x01>;
linux,code = <0x211>;
debounce-interval = <0x3c>;
gpios = <0x0d 0x26 0x01>;
};
};
bt@7000000 {
clock-names = "lpo_clk";
reg-names = "bt_warm_rst";
resets = <0x0b 0x08>;
memory-region = <0x31>;
interrupts = <0x00 0xa2 0x01>;
clocks = <0x0b 0x24>;
compatible = "qcom,bt";
status = "ok";
firmware = "IPQ5018/bt_fw_patch.mdt";
reg = <0x1943008 0x08>;
reset-names = "btss_reset";
qcom,ipc = <0x30 0x08 0x17>;
bt_maple {
compatible = "qcom,maple-bt";
status = "disabled";
};
};
cti@6014000 {
arm,primecell-periphid = <0x3b966>;
clock-names = "apb_pclk\0core_a_clk";
reg-names = "cti-base";
clocks = <0x0b 0x61 0x0b 0x5e>;
coresight-name = "coresight-cti4";
compatible = "arm,primecell";
reg = <0x6014000 0x1000>;
};
ssuniphy@5d000 {
clock-names = "pipe_clk\0phy_cfg_ahb_clk";
resets = <0x0b 0x63>;
clocks = <0x0b 0xc5 0x0b 0x8f>;
#phy-cells = <0x00>;
compatible = "qca,ipq5018-uni-ssphy";
status = "ok";
reg = <0x5d000 0x800>;
phandle = <0x21>;
reset-names = "por_rst";
};
qcom,apss_clk@b111000 {
#reset-cells = <0x01>;
#clock-cells = <0x01>;
compatible = "qcom,apss-ipq5018";
reg = <0xb111000 0x6000>;
};
nss@40000000 {
qcom,gre-enabled;
qcom,pppoe-enabled;
qcom,low-frequency = <0x32a9f880>;
clock-names = "nss-cfg-clk\0nss-dbg-clk\0nss-core-clk\0nss-utcm-clk\0nss-axi-clk\0nss-snoc-axi-clk\0nss-nc-axi-clk";
reg-names = "nphys\0qgic-phys";
qcom,crypto-enabled;
qcom,id = <0x00>;
qcom,map-t-enabled;
qcom,l2tpv2-enabled;
qcom,max-frequency = <0x3b9aca00>;
interrupts = <0x00 0x192 0x01 0x00 0x191 0x01 0x00 0x190 0x01 0x00 0x18f 0x01 0x00 0x18e 0x01 0x00 0x18d 0x01 0x00 0x18c 0x01 0x00 0x18b 0x01>;
clocks = <0x0b 0x81 0x0b 0x83 0x0b 0x82 0x0b 0x85 0x0b 0x80 0x0b 0x76 0x0b 0x84>;
qcom,pvxlan-enabled;
qcom,mirror-enabled;
qcom,wlanredirect-enabled;
qcom,ipv4-enabled;
qcom,pptp-enabled;
qcom,gre-redir-mark-enabled;
qcom,tun6rd-enabled;
compatible = "qcom,nss";
qcom,clmap-enabled;
qcom,num-pri = <0x04>;
qcom,load-addr = <0x40000000>;
qcom,ipv6-enabled;
qcom,udp-st-enabled;
qcom,gre-redir-enabled;
qcom,ipv6-reasm-enabled;
qcom,shaping-enabled;
reg = <0x7a00000 0x100 0xb111000 0x1000>;
qcom,tunipip6-enabled;
qcom,num-queue = <0x04>;
qcom,mid-frequency = <0x32a9f880>;
qcom,ipv4-reasm-enabled;
qcom,ipsec-enabled;
qcom,portid-enabled;
qcom,wlan-dataplane-offload-enabled;
qcom,match-enabled;
qcom,vxlan-enabled;
qcom,num-irq = <0x08>;
};
cti@6011000 {
arm,primecell-periphid = <0x3b966>;
clock-names = "apb_pclk\0core_a_clk";
reg-names = "cti-base";
clocks = <0x0b 0x61 0x0b 0x5e>;
coresight-name = "coresight-cti1";
compatible = "arm,primecell";
reg = <0x6011000 0x1000>;
};
tpdm@6110000 {
arm,primecell-periphid = <0x3b968>;
clock-names = "apb_pclk\0core_a_clk";
reg-names = "tpdm-base";
clocks = <0x0b 0x61 0x0b 0x5e>;
coresight-name = "coresight-tpdm-dcc";
compatible = "arm,primecell";
reg = <0x6110000 0x1000>;
port {
endpoint {
remote-endpoint = <0x53>;
phandle = <0x52>;
};
};
};
funnel@6041000 {
arm,primecell-periphid = <0xbb908>;
clock-names = "apb_pclk\0core_a_clk";
reg-names = "funnel-base";
clocks = <0x0b 0x61 0x0b 0x5e>;
coresight-name = "coresight-funnel-in0";
compatible = "arm,primecell";
reg = <0x6041000 0x1000>;
ports {
#address-cells = <0x01>;
#size-cells = <0x00>;
port@0 {
reg = <0x00>;
endpoint {
remote-endpoint = <0x3b>;
phandle = <0x3a>;
};
};
port@5 {
reg = <0x07>;
endpoint {
slave-mode;
remote-endpoint = <0x40>;
phandle = <0x4f>;
};
};
port@3 {
reg = <0x05>;
endpoint {
slave-mode;
remote-endpoint = <0x3e>;
phandle = <0x46>;
};
};
port@1 {
reg = <0x03>;
endpoint {
slave-mode;
remote-endpoint = <0x3c>;
phandle = <0x42>;
};
};
port@6 {
reg = <0x00>;
endpoint {
slave-mode;
remote-endpoint = <0x41>;
phandle = <0x4e>;
};
};
port@4 {
reg = <0x06>;
endpoint {
slave-mode;
remote-endpoint = <0x3f>;
phandle = <0x51>;
};
};
port@2 {
reg = <0x04>;
endpoint {
slave-mode;
remote-endpoint = <0x3d>;
phandle = <0x44>;
};
};
};
};
gcc@1800000 {
#reset-cells = <0x01>;
clock-names = "xo\0sleep_clk";
clocks = <0x17 0x18>;
#clock-cells = <0x01>;
compatible = "qcom,gcc-ipq5018";
reg = <0x1800000 0x80000>;
phandle = <0x0b>;
};
sdhci@7804000 {
clock-names = "iface\0core";
reg-names = "hc_mem";
mmc-hs200-1_8v;
bus-width = <0x04>;
non-removable;
interrupts = <0x00 0x7b 0x04 0x00 0x8a 0x04>;
clocks = <0x0b 0x6b 0x0b 0x6c>;
mmc-ddr-1_8v;
compatible = "qcom,sdhci-msm-v5";
status = "disabled";
interrupt-names = "hc_irq\0pwr_irq";
reg = <0x7804000 0x1000>;
max-frequency = <0xb71b000>;
};
wifi@c000000 {
qcom,tgt-mem-mode = <0x01>;
qcom,caldb-addr = <0x4c900000 0x4c900000 0x00 0x00 0x00 0x00>;
interrupts = <0x00 0x120 0x01 0x00 0x121 0x01 0x00 0x122 0x01 0x00 0x124 0x01 0x00 0x125 0x01 0x00 0x126 0x01 0x00 0x127 0x01 0x00 0x128 0x01 0x00 0x129 0x01 0x00 0x12a 0x01 0x00 0x12b 0x01 0x00 0x12c 0x01 0x00 0x12d 0x01 0x00 0x12e 0x01 0x00 0x12f 0x01 0x00 0x130 0x01 0x00 0x131 0x01 0x00 0x132 0x01 0x00 0x133 0x01 0x00 0x134 0x01 0x00 0x135 0x01 0x00 0x136 0x01 0x00 0x137 0x01 0x00 0x14e 0x01 0x00 0x139 0x01 0x00 0x13a 0x01 0x00 0x13b 0x01 0x00 0x13c 0x01 0x00 0x13d 0x01 0x00 0x13e 0x01 0x00 0x13f 0x01 0x00 0x140 0x01 0x00 0x141 0x01 0x00 0x142 0x01 0x00 0x143 0x01 0x00 0x144 0x01 0x00 0x145 0x01 0x00 0x146 0x01 0x00 0x147 0x01 0x00 0x148 0x01 0x00 0x149 0x01 0x00 0x14a 0x01 0x00 0x14b 0x01 0x00 0x14c 0x01 0x00 0x14d 0x01 0x00 0x138 0x01 0x00 0x14f 0x01 0x00 0x156 0x01 0x00 0x150 0x01 0x00 0x151 0x01 0x00 0x152 0x01 0x00 0x153 0x01>;
qcom,rproc = <0x2e>;
qcom,board_id = <0x24>;
compatible = "qcom,cnss-qca5018\0qcom,ipq5018-wifi";
status = "ok";
qcom,caldb-size = <0x200000>;
interrupt-names = "misc-pulse1\0misc-latch\0sw-exception\0ce0\0ce1\0ce2\0ce3\0ce4\0ce5\0ce6\0ce7\0ce8\0ce9\0ce10\0ce11\0host2wbm-desc-feed\0host2reo-re-injection\0host2reo-command\0host2rxdma-monitor-ring3\0host2rxdma-monitor-ring2\0host2rxdma-monitor-ring1\0reo2ost-exception\0wbm2host-rx-release\0reo2host-status\0reo2host-destination-ring4\0reo2host-destination-ring3\0reo2host-destination-ring2\0reo2host-destination-ring1\0rxdma2host-monitor-destination-mac3\0rxdma2host-monitor-destination-mac2\0rxdma2host-monitor-destination-mac1\0ppdu-end-interrupts-mac3\0ppdu-end-interrupts-mac2\0ppdu-end-interrupts-mac1\0rxdma2host-monitor-status-ring-mac3\0rxdma2host-monitor-status-ring-mac2\0rxdma2host-monitor-status-ring-mac1\0host2rxdma-host-buf-ring-mac3\0host2rxdma-host-buf-ring-mac2\0host2rxdma-host-buf-ring-mac1\0rxdma2host-destination-ring-mac3\0rxdma2host-destination-ring-mac2\0rxdma2host-destination-ring-mac1\0host2tcl-input-ring4\0host2tcl-input-ring3\0host2tcl-input-ring2\0host2tcl-input-ring1\0wbm2host-tx-completions-ring4\0wbm2host-tx-completions-ring3\0wbm2host-tx-completions-ring2\0wbm2host-tx-completions-ring1\0tcl2host-status-ring";
reg = <0xc000000 0x1000000>;
mem-region = <0x2b>;
qcom,bdf-addr = <0x4ba00000 0x4ba00000 0x4ba00000 0x00 0x00 0x00>;
};
ess-uniphy@98000 {
compatible = "qcom,ess-uniphy";
status = "disabled";
reg = <0x98000 0x800>;
uniphy_access_mode = "local bus";
};
timer {
interrupts = <0x01 0x02 0xf08 0x01 0x03 0xf08 0x01 0x04 0xf08 0x01 0x01 0xf08>;
compatible = "arm,armv8-timer";
};
dbgui@6108000 {
qcom,dbgui-addr-offset = <0x30>;
clock-names = "apb_pclk\0core_a_clk";
reg-names = "dbgui-base";
clocks = <0x0b 0x61 0x0b 0x5e>;
coresight-name = "coresight-dbgui";
compatible = "qcom,coresight-dbgui";
reg = <0x6108000 0x1000>;
qcom,dbgui-size = <0x40>;
qcom,dbgui-data-offset = <0x130>;
port {
endpoint {
remote-endpoint = <0x50>;
phandle = <0x43>;
};
};
};
thermal-sensor@4a9000 {
nvmem-cells = <0x54>;
#qcom,sensors = <0x05>;
interrupts = <0x00 0xb8 0x01>;
#thermal-sensor-cells = <0x01>;
compatible = "qcom,ipq5018-tsens";
nvmem-cell-names = "calib";
reg = <0x4a9000 0x1000 0x4a8000 0x1000>;
phandle = <0x59>;
};
pcm_lb@0 {
compatible = "qca,ipq5018-pcm-lb";
status = "disabled";
};
rpm_etm0 {
qcom,inst-id = <0x04>;
coresight-name = "coresight-rpm-etm0";
compatible = "qcom,coresight-remote-etm";
status = "disabled";
port {
endpoint {
remote-endpoint = <0x4e>;
phandle = <0x41>;
};
};
};
dma@7984000 {
clock-names = "bam_clk";
interrupts = <0x00 0x92 0x04>;
clocks = <0x0b 0x67>;
compatible = "qcom,bam-v1.7.0";
status = "ok";
reg = <0x7984000 0x1c000>;
phandle = <0x1d>;
qcom,ee = <0x00>;
#dma-cells = <0x01>;
};
csr@6001000 {
qcom,set-byte-cntr-support;
qcom,blk-size = <0x01>;
clock-names = "apb_pclk\0core_a_clk";
reg-names = "csr-base";
clocks = <0x0b 0x61 0x0b 0x5e>;
coresight-name = "coresight-csr";
compatible = "qcom,coresight-csr";
reg = <0x6001000 0x1000>;
phandle = <0x35>;
};
pcm@0xA3C0000 {
pinctrl-names = "default";
voice_loopback = <0x00>;
pinctrl-0 = <0x32>;
interrupts = <0x00 0x1b 0x04>;
capture_memory = "lpm";
compatible = "qca,ipq5018-lpass-pcm";
status = "disabled";
interrupt-names = "out0";
playback_memory = "lpm";
reg = <0xa3c0000 0x23014>;
};
etm@619c000 {
arm,primecell-periphid = <0xbb95d>;
clock-names = "apb_pclk\0core_a_clk";
clocks = <0x0b 0x61 0x0b 0x5e>;
cpu = <0x4a>;
coresight-name = "coresight-etm0";
compatible = "arm,primecell";
reg = <0x619c000 0x1000>;
port {
endpoint {
remote-endpoint = <0x4b>;
phandle = <0x48>;
};
};
};
cti@601f000 {
arm,primecell-periphid = <0x3b966>;
clock-names = "apb_pclk\0core_a_clk";
reg-names = "cti-base";
clocks = <0x0b 0x61 0x0b 0x5e>;
coresight-name = "coresight-cti15";
compatible = "arm,primecell";
reg = <0x601f000 0x1000>;
};
tmc@6048000 {
arm,buffer-size = <0x100000>;
arm,primecell-periphid = <0xbb961>;
coresight-ctis = <0x33 0x34>;
funnel-address = <0x6041000 0x1000>;
arm,scatter-gather;
clock-names = "apb_pclk\0core_a_clk";
reg-names = "tmc-base\0bam-base";
memory-region = <0x2c>;
interrupts = <0x00 0xa6 0x01>;
clocks = <0x0b 0x61 0x0b 0x5e>;
coresight-name = "coresight-tmc-etr";
compatible = "arm,primecell";
interrupt-names = "byte-cntr-irq";
reg = <0x6048000 0x1000 0x6064000 0x15000>;
coresight-csr = <0x35>;
port {
endpoint {
slave-mode;
remote-endpoint = <0x36>;
phandle = <0x37>;
};
};
};
funnel@6100000 {
arm,primecell-periphid = <0xbb908>;
clock-names = "apb_pclk\0core_a_clk";
reg-names = "funnel-base";
clocks = <0x0b 0x61 0x0b 0x5e>;
coresight-name = "coresight-funnel-center";
compatible = "arm,primecell";
reg = <0x6100000 0x1000>;
ports {
#address-cells = <0x01>;
#size-cells = <0x00>;
port@0 {
reg = <0x00>;
endpoint {
remote-endpoint = <0x42>;
phandle = <0x3c>;
};
};
port@1 {
reg = <0x02>;
endpoint {
slave-mode;
remote-endpoint = <0x43>;
phandle = <0x50>;
};
};
};
};
cti@601c000 {
arm,primecell-periphid = <0x3b966>;
clock-names = "apb_pclk\0core_a_clk";
reg-names = "cti-base";
clocks = <0x0b 0x61 0x0b 0x5e>;
coresight-name = "coresight-cti12";
compatible = "arm,primecell";
reg = <0x601c000 0x1000>;
};
cti@6199000 {
arm,primecell-periphid = <0x3b966>;
clock-names = "apb_pclk\0core_a_clk";
reg-names = "cti-base";
clocks = <0x0b 0x61 0x0b 0x5e>;
cpu = <0x4c>;
coresight-name = "coresight-cti-cpu1";
compatible = "arm,primecell";
reg = <0x6199000 0x1000>;
};
dp1 {
phy-mode = "sgmii";
clock-names = "nss-snoc-gmac-axi-clk";
qcom,id = <0x01>;
mdio-bus = <0x55>;
local-mac-address = [00 00 00 00 00];
qcom,phy-mdio-addr = <0x07>;
interrupts = <0x00 0x65 0x04>;
clocks = <0x0b 0x6f>;
device_type = "network";
qcom,rx-page-mode = <0x00>;
compatible = "qcom,nss-dp";
qcom,mactype = <0x02>;
reg = <0x39c00000 0x10000>;
qcom,link-poll = <0x01>;
};
syscon@b111000 {
compatible = "syscon";
reg = <0xb111000 0x1000>;
phandle = <0x30>;
};
qcom,diag@0 {
status = "ok";
};
pwm@0x1941010 {
clock-names = "core";
src-freq = <0x5f5e100>;
clocks = <0x0b 0xcb>;
compatible = "qti,ipq5018-pwm";
status = "disabled";
reg = <0x1941010 0x20>;
pwm-base-index = <0x00>;
used-pwm-indices = <0x01 0x01 0x01 0x01>;
};
wcss-smp2p {
qcom,local-pid = <0x00>;
interrupts = <0x00 0xb1 0x01>;
interrupt-parent = <0x01>;
qcom,remote-pid = <0x01>;
global_timer = "\0JP";
compatible = "qcom,smp2p";
status = "ok";
mboxes = <0x04 0x09>;
qcom,smem = <0x1b3 0x1ac>;
slave-kernel {
qcom,entry-name = "slave-kernel";
#interrupt-cells = <0x02>;
phandle = <0x28>;
interrupt-controller;
};
master-kernel {
qcom,entry-name = "master-kernel";
qcom,smp2p-feature-ssr-ack;
#qcom,smem-state-cells = <0x01>;
phandle = <0x2a>;
};
};
hwevent@6101000 {
clock-names = "apb_pclk\0core_a_clk";
reg-names = "center-wrapper-mux\0center-wrapper-lockaccess\0right-wrapper-mux\0right-wrapper-lockaccess\0mm-wrapper-mux\0mm-wrapper-lockaccess\0mm-fun-lockaccess\0mm-fun\0in-fun-lockaccess\0in-fun";
clocks = <0x0b 0x61 0x0b 0x5e>;
coresight-name = "coresight-hwevent";
compatible = "qcom,coresight-hwevent";
reg = <0x6101000 0x148 0x6101fb0 0x04 0x6121000 0x148 0x6121fb0 0x04 0x6131000 0x148 0x6131fb0 0x04 0x6130fb0 0x04 0x6130000 0x148 0x6041fb0 0x04 0x6041000 0x148>;
};
dma@7884000 {
clock-names = "bam_clk";
interrupts = <0x00 0xee 0x04>;
clocks = <0x0b 0x19>;
compatible = "qcom,bam-v1.7.0";
reg = <0x7884000 0x1d000>;
phandle = <0x1a>;
qcom,ee = <0x00>;
#dma-cells = <0x01>;
};
cti@6019000 {
arm,primecell-periphid = <0x3b966>;
clock-names = "apb_pclk\0core_a_clk";
reg-names = "cti-base";
clocks = <0x0b 0x61 0x0b 0x5e>;
coresight-name = "coresight-cti9";
compatible = "arm,primecell";
reg = <0x6019000 0x1000>;
};
pci@80000000 {
pinctrl-names = "default";
#address-cells = <0x03>;
phy-names = "pciephy";
bus-range = <0x00 0xff>;
pinctrl-0 = <0x24 0x25>;
clock-names = "iface\0axi_m\0axi_s\0ahb\0aux\0axi_bridge";
reg-names = "dbi\0elbi\0atu\0parf\0config\0system_noc";
axi-halt-val = <0x1e>;
resets = <0x0b 0x31 0x0b 0x32 0x0b 0x33 0x0b 0x34 0x0b 0x35 0x0b 0x36 0x0b 0x37 0x0b 0x38>;
interrupts = <0x00 0x77 0x04>;
clocks = <0x0b 0x78 0x0b 0x51 0x0b 0x53 0x0b 0x4f 0x0b 0x50 0x0b 0x52>;
interrupt-map = <0x00 0x00 0x00 0x01 0x01 0x00 0x8e 0x04 0x00 0x00 0x00 0x02 0x01 0x00 0x8f 0x04 0x00 0x00 0x00 0x03 0x01 0x00 0x90 0x04 0x00 0x00 0x00 0x04 0x01 0x00 0x91 0x04>;
#size-cells = <0x02>;
device_type = "pci";
interrupt-map-mask = <0x00 0x00 0x00 0x07>;
interrupts-extended = <0x0d 0x13 0x00 0x0d 0x00 0x00 0x01 0x00 0x77 0x04>;
num-lanes = <0x01>;
compatible = "qcom,pcie-ipq5018";
slot_id = <0x00>;
ranges = <0x81000000 0x00 0x80200000 0x80200000 0x00 0x100000 0x82000000 0x00 0x80300000 0x80300000 0x00 0x10000000>;
#interrupt-cells = <0x01>;
status = "ok";
interrupt-names = "wake_gpio\0mdm2ap_e911\0global_irq";
phys = <0x22>;
reg = <0x80000000 0xf1d 0x80000f20 0xa8 0x80001000 0x1000 0x78000 0x3000 0x80100000 0x1000 0x560508 0x04>;
linux,pci-domain = <0x00>;
msi-parent = <0x23>;
reset-names = "pipe\0sleep\0sticky\0axi_m\0axi_s\0ahb\0axi_m_sticky\0axi_s_sticky";
perst-gpio = <0x0d 0x12 0x01>;
e911-gpio = <0x0d 0x00 0x00>;
pcie_x1_rp {
reg = <0x00 0x00 0x00 0x00 0x00>;
};
};
cti@6016000 {
arm,primecell-periphid = <0x3b966>;
clock-names = "apb_pclk\0core_a_clk";
reg-names = "cti-base";
clocks = <0x0b 0x61 0x0b 0x5e>;
coresight-name = "coresight-cti6";
compatible = "arm,primecell";
reg = <0x6016000 0x1000>;
};
serial@78af000 {
tx-watermark = <0x00>;
clock-names = "core\0iface";
interrupts = <0x00 0x6b 0x04>;
clocks = <0x0b 0x21 0x0b 0x19>;
compatible = "qcom,msm-uartdm-v1.4\0qcom,msm-uartdm";
status = "ok";
reg = <0x78af000 0x200>;
};
mdio@90000 {
pinctrl-names = "default";
phy-reset-gpio = <0x0d 0x27 0x00>;
#address-cells = <0x01>;
pinctrl-0 = <0x0c>;
#size-cells = <0x01>;
compatible = "qcom,qca-mdio";
status = "ok";
reg = <0x90000 0x64>;
phandle = <0x14>;
ethernet-phy@3 {
reg = <0x03>;
phandle = <0x12>;
};
ethernet-phy@1 {
reg = <0x01>;
phandle = <0x10>;
};
switch0@10 {
#address-cells = <0x01>;
#size-cells = <0x00>;
compatible = "qca,qca8337";
reg = <0x10>;
ports {
#address-cells = <0x01>;
#size-cells = <0x00>;
port@0 {
phy-mode = "sgmii";
label = "cpu";
reg = <0x06>;
ethernet = <0x0e>;
fixed-link {
full-duplex;
speed = <0x3e8>;
};
};
port@3 {
label = "lan3";
reg = <0x03>;
phy-handle = <0x11>;
};
port@1Pokaż co ci się udało odpalić w ramie.
https://drive.google.com/file/d/1b12DCF … sp=sharing
ten obraz odpalił i pokazał przynajmniej konsole
24.10 nie ma wsparcia dla ipq50xx. Więc co kompilujesz? Przeportowałeś całą obsługę nowej architektury na wydanie stabilne?
Może dlatego nie chce za boga się skompilować kernel 
to jedyna opcja to snapshot? jakiegoś udało mi się skompilować i wrzucić w ram i odpalił konsole
Ucichł coś temat. Ktoś coś z tym robi?
Ja cały czas próbuje zbudować 24.10 ale walczę z błędami kompilacji różnego rodzaju a czasu nie mam 24/7
Powiem tak zbudowałem obraz który się uruchomił z ramu co prawda na snapie r0-2c667f2 ale to już jakiś krok przynajmniej przywitał mnie konsolą na więcej testów nie mam czasu dziś jutro wracam do tematu popołudniem i zobaczę co poza konsolą działa ;p a na noc zostawię kompilacje na 24.10
Sam utrudniasz sobie życie
Tak, to inna wersja. Czy zrobiłeś wcześniej backup partycji tego co miałeś w routerze?
Czy sam to nwm raczej mechanizm działania MacBooka tak kopie mam
Odkryłem dlaczego nie mogłem zrobić flash przez www z ubota problemem okazało się przechowywanie danych na icloud ;p wybranie pliku nie przesyłało go poprawnie do przeglądarki ale nie o tym ciekawsze jest to że zrobiłem flash tym softem od z yt i co ciekawe to jest prawdopodobnie inny bild bo ma zmienioną nazwę wersji
Wersja firmware：OpenWrt 23.05-AliExpress ZEARTS Store
co jak myśle oznacza że sprzedawca ma config do tego cuda
Dzień dobry. Na reddicie była dyskusja na temat D50 https://www.reddit.com/r/openwrt/commen … gacy-sct=1
Ktoś wstawił nawet FW. Podobno działa, tylko jakiś problem z wifi jest
https://drive.google.com/file/d/18ZGxBs … xgERL/view
Coś mi się wydaje że to jest fw od chińczyka które lata po internecie a nie jest to kompilacja własna jeśli chodzi o problemy z działaniem pojawiają sie jak ktoś zaktualizuje wszystkie pakiety to rzeczywiście nie działa ;P
To może być ciągle kwestia rozmiaru , pamiętam w AW1000 , że te "z wszystkim" jako initramfs sie nie uruchamiały , bo po prostu były za duże ,a 15Mb dla wersji min to ciągle sporo...
Może załadowanie trochę niżej , np do adresu 43000000 pomoże ?
Sprawdzę chociaż możesz mieć rację jak próbowałem załadować partycje roota to również nie pozwalał załadować jej w całości żeby zrzucić przez tftp jako backup
OK, kasuję obrazu i wymaga to indywidualizowanej pracy z urządzeniem.
Mogę jeszcze jakoś pomóc czy na tym kończy się ta misja?
Zmieniłem, skompilowałem, @ArTu sprawdź plik jeszcze raz z https://dl.eko.one.pl/test/xunison-exigo-d50-5g/min/
## Loading kernel from FIT Image at 44000000 ...
Using 'config@mp03.1' configuration
Trying 'kernel-1' kernel subimage
Description: ARM64 OpenWrt Linux-6.12.57
Type: Kernel Image
Compression: gzip compressed
Data Start: 0x440000e8
Data Size: 15205687 Bytes = 14.5 MiB
Architecture: AArch64
OS: Linux
Load Address: 0x41000000
Entry Point: 0x41000000
Hash algo: crc32
Hash value: 5a71a454
Hash algo: sha1
Hash value: fec6ab508df21c609508e2b55df44bf4f10960c6
Verifying Hash Integrity ... crc32+ sha1+ OK
## Loading fdt from FIT Image at 44000000 ...
Using 'config@mp03.1' configuration
Trying 'fdt-1' fdt subimage
Description: ARM64 OpenWrt brax,fa532 device tree blob
Type: Flat Device Tree
Compression: uncompressed
Data Start: 0x44e8075c
Data Size: 46728 Bytes = 45.6 KiB
Architecture: AArch64
Hash algo: crc32
Hash value: 8fed4373
Hash algo: sha1
Hash value: f4305143c1e50c361843dd2ebe49b9dd0843afdb
Verifying Hash Integrity ... crc32+ sha1+ OK
Booting using the fdt blob at 0x44e8075c
Uncompressing Kernel Image ... OK
Loading Device Tree to 4a3f1000, end 4a3ff687 ... OK
Could not find PCI in device tree
Using machid 0x8040001 from environment
Starting kernel ...
Jumping to AARCH64 kernel via monitor
Format: Log Type - Time(microsec) - Message - Optional Info
Log Type: B - Since Boot(Power On Reset), D - Delta, S - Statistic
S - QC_IMAGE_VERSION_STRING=BOOT.BF.3.3.1.1-00066
S - IMAGE_VARIANT_STRING=MAACANAZA
S - OEM_IMAGE_VERSION_STRING=CRM
S - Boot Config, 0x000002c5
B - 126 - PBL, Start
B - 1557 - bootable_media_detect_entry, Start
B - 3347 - bootable_media_detect_success, Start
B - 3350 - elf_loader_entry, Start
B - 8514 - auth_hash_seg_entry, Start
B - 8874 - auth_hash_seg_exit, Start
B - 100500 - elf_segs_hash_verify_entry, Start
B - 170061 - PBL, End
B - 139903 - SBL1, Start
B - 201269 - GCC [RstStat:0x10, RstDbg:0x500100] WDog Stat : 0x4
B - 209596 - clock_init, Start
D - 7442 - clock_init, Delta
B - 217190 - boot_flash_init, Start
D - 14945 - boot_flash_init, Delta
B - 232196 - boot_config_data_table_init, Start
D - 4666 - boot_config_data_table_init, Delta - (575 Bytes)
B - 239943 - Boot Setting : 0x00000618
B - 246318 - CDT version:2,Platform ID:8,Major ID:4,Minor ID:0,Subtype:1
B - 253028 - sbl1_ddr_set_params, Start
B - 254461 - Pre_DDR_clock_init, Start
B - 260317 - Pre_DDR_clock_init, End
B - 902556 - do ddr sanity test, Start
D - 30 - do ddr sanity test, Delta
B - 907222 - Image Load, Start
D - 242871 - QSEE Image Loaded, Delta - (578956 Bytes)
B - 1150917 - Image Load, Start
D - 13878 - DEVCFG Image Loaded, Delta - (13592 Bytes)
B - 1164825 - Image Load, Start
D - 196024 - APPSBL Image Loaded, Delta - (470282 Bytes)
B - 1360910 - QSEE Execution, Start
D - 61 - QSEE Execution, Delta
B - 1367376 - SBL1, End
D - 1230126 - SBL1, Delta
S - Flash Throughput, 2457 KB/s (1064077 Bytes, 433062 us)
S - DDR Frequency, 800 MHz
S - Core 0 Frequency, 800 MHz
U-Boot 2016.01 (Mar 19 2025 - 18:39:12 +0800)
DRAM: smem ram ptable found: ver: 1 len: 4
512 MiB
NAND: QPIC controller support serial NAND
ID = 7f7f11c8
Vendor = c8
Device = 11
Serial Nand Device Found With ID : 0xc8 0x11
Serial NAND device Manufacturer:F50D1G41LB(2M)
Device Size:128 MiB, Page size:2048, Spare Size:64, ECC:4-bit
SF: Unsupported flash IDs: manuf 00, jedec 0000, ext_jedec 0000
ipq_spi: SPI Flash not found (bus/cs/speed/mode) = (0/0/48000000/0)
128 MiB
MMC: sdhci: Node Not found, skipping initialization
PCI Link Intialized
PCI1 is not defined in the device tree
In: serial@78AF000
Out: serial@78AF000
Err: serial@78AF000
machid: 8040001
Reset button GPIO: 22
Web LED GPIO: 1
###### PULL UP GPIO31 for MODEM POWER UP
Hit any key to stop autoboot: 5 4 3 2 1 0
ubi0: attaching mtd1
ubi0: scanning is finished
ubi0: attached mtd1 (name "mtd=0", size 58 MiB)
ubi0: PEB size: 131072 bytes (128 KiB), LEB size: 126976 bytes
ubi0: min./max. I/O unit sizes: 2048/2048, sub-page size 2048
ubi0: VID header offset: 2048 (aligned 2048), data offset: 4096
ubi0: good PEBs: 464, bad PEBs: 0, corrupted PEBs: 0
ubi0: user volume: 3, internal volumes: 1, max. volumes count: 128
ubi0: max/mean erase counter: 111/25, WL threshold: 4096, image sequence number: 1014258347
ubi0: available PEBs: 0, total reserved PEBs: 464, PEBs reserved for bad PEB handling: 20
Read 0 bytes from volume kernel to 44000000
No size specified -> Using max size (4952064)
## Loading kernel from FIT Image at 44000000 ...
Using 'config@mp03.1' configuration
Trying 'kernel@1' kernel subimage
Description: ARM64 OpenWrt Linux-5.4.213
Type: Kernel Image
Compression: gzip compressed
Data Start: 0x440000e8
Data Size: 4829324 Bytes = 4.6 MiB
Architecture: AArch64
OS: Linux
Load Address: 0x41080000
Entry Point: 0x41080000
Hash algo: crc32
Hash value: 98e0a012
Hash algo: sha1
Hash value: 3ec53903b8e5a74770f1b1109e244d28db895126
Verifying Hash Integrity ... crc32+ sha1+ OK
## Loading fdt from FIT Image at 44000000 ...
Using 'config@mp03.1' configuration
Trying 'fdt@1' fdt subimage
Description: ARM64 OpenWrt brax_fa532 device tree blob
Type: Flat Device Tree
Compression: uncompressed
Data Start: 0x4449b2b0
Data Size: 45055 Bytes = 44 KiB
Architecture: AArch64
Hash algo: crc32
Hash value: 0672e5f1
Hash algo: sha1
Hash value: 68c6c31919b811771705d1d9c9a83ffbea18c485
Verifying Hash Integrity ... crc32+ sha1+ OK
Booting using the fdt blob at 0x4449b2b0
Uncompressing Kernel Image ... OK
Loading Device Tree to 4a3f2000, end 4a3ffffe ... OK
Could not find PCI in device tree
Using machid 0x8040001 from environment
Starting kernel ...
Jumping to AARCH64 kernel via monitor
[ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x51af8014]
[ 0.000000] Linux version 5.4.213 (lingjp@lingjp) (gcc version 12.3.0 (OpenWrt GCC 12.3.0 r0-db4361aef)) #0 SMP PREEMPT Sun Dec 15 07:22:42 2024
[ 0.000000] Machine model: D50 5Gczy czasem Could not find PCI in device tree nie będzie problemem?
coś stronka się chyba sypła bo dzisiaj jak wklejam i zapisuje to dostaje pusty link
Alternatywny link https://zerobin.net/?a15027e6be6d5a2b#K … bJ4Ss73PI=
Niestety ale obraz nie wstaje
Log: https://pastebin.com/JrXfwD5s
Udało mi się odpalić tftp i poprzez niego wgrać do ramu pod wcześniej wskazany adres
No to musisz palcem pokazać , bo ja nie widzę loga z tego , ani jak robiłeś tego pena
Wybacz faktynie tego logu nie wrzuciłem na szybko wyciągam co mam z kopiowanych logów do AI
athrs17_reg_init: complete athrs17_vlan_config …done S17c init done board_update_caldata: Unable to find slot-Id, Default CapIn/CapOut values used eth0, eth1 IPQ5018# usb start starting USB… USB0: Register 2000140 NbrPorts 2 Starting the controller USB XHCI 1.10 scanning bus 0 for devices… 1 USB Device(s) found IPQ5018#USB device tree: 1 Hub (5 Gb/s, 0mA)
| U-Boot XHCI Host Controller
|
|+-2 Vendor specific (480 Mb/s, 500mA)
Quectel RM500Q-AE 1a0d52e8
IPQ5018#Panowie jak pisałem będę walczył dalej wieczorem lub nocą
Uboot z USB nie widzi pendrive jedynie modem fatls USB 0 sprawdzałem do 5 daje wynik brak urządzenia czy błędne urządzenie jest to w logach z wczoraj
ArTu napisał/a:MiG25 napisał/a:a skąd ten adres 0x82000000 wziąłeś ? Może samo "tftpboot test.bin" zadziała ...
Hehe z podpowiedzi AI ???? które kazało mi sprawdzić różne adresy iiii stwierdziło na koniec że to zablokowane ???? ja na dziś odpuszczam o 4 wstaje do roboty ???? powrócę do zabawy jutro.
Natomiast ja mam jeszcze pytanie za 100 pkt jak zrobię wylut pamięci i odczytam ją bezpośrednio programatorem to mogę mieć w d** zabawę z tymi ubotami ???? bo jak się wkurzę to tak zrobię i bd modyfikować na żywca jak padnie to wgram programatorem do kości i jazda na nowo ????Generalnie tak, możesz odlutować i zgrać/wgrać nowy soft. Ale docelowo to nie jest sposób - bo to nie jest możliwość dla wszystkich. O ile wgrywanie przez uboota jeszcze ujdzie to zabawa z programatorem jest już dla super zaawansowanych i wielu sobie z tym nie poradzi.
Także męcz tego uboota.BTW. A czemu po prostu nie wgrywasz z softu jako aktualizację? Ja wiem że trzeba recovery opanować, ale dlaczego nie próbowałeś wgrać przez luci tak po prostu?
Wgrać mogę ale nie chce mieć ładnej doniczki jak nie opanuje jak wgrać soft przez uboota to jak dobrze rozumiem jak soft nie wgra się prawidłowo to będzie cegiełka i jakoś chciałbym mieć możliwość powrotu nawet jeśli programator to tymczasowe rozwiązanie to w czasie kiedy bd walczył z ubotem może ktoś będzie w stanie poprawić soft jeśli coś pójdzie nie tak jak powinno jako amator to ciężko się za to zabrać wszystko samemu i w jednym czasie mając też ograniczony zasób czasu a myślę że normalny soft przyda się nie tylko mi bo tak naprawdę jedyne czego obecnie mi brak to Wireguarda ale też nie jest to na tyle paląca kwestia żeby stawać na głowie bardziej zależało mi na 5g bo zrezygnowałem z światłowodu orange ze względu na ich zagrania z przedłużaniem umowy ale to długi nudny temat. dziś wieczorem/ w nocy postaram się pomęczyć uboota a jeśli mi to nie wyjdzie to rwę pamięć i odczytuje programatorem o ile svod sobie z tym poradzi bo może z 1 w życiu póki co korzystałem z tej funkcji
Ładuje z adresu 0x44000000. Jest to w logach.
Mądrego to dobrze i posłuchać :) jutro sprawdzę
a skąd ten adres 0x82000000 wziąłeś ? Może samo "tftpboot test.bin" zadziała ...
Hehe z podpowiedzi AI ???? które kazało mi sprawdzić różne adresy iiii stwierdziło na koniec że to zablokowane ???? ja na dziś odpuszczam o 4 wstaje do roboty ???? powrócę do zabawy jutro.
Natomiast ja mam jeszcze pytanie za 100 pkt jak zrobię wylut pamięci i odczytam ją bezpośrednio programatorem to mogę mieć w d** zabawę z tymi ubotami ???? bo jak się wkurzę to tak zrobię i bd modyfikować na żywca jak padnie to wgram programatorem do kości i jazda na nowo ????
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